Compact Memory Cell Combining SRAM Access and Resistive Retention
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Solution Overview
Problem
Current memory technologies face challenges such as volatility in SRAM, slowness and high voltage requirements in flash memory, and integration difficulties with CMOS, along with the need for compact and fast non-volatile data storage solutions.
Innovation Solution
A memory cell design incorporating a resistance switching element that stores non-volatile data, allowing for quick access and low power consumption by leveraging leakage currents and resistive states, combined with a compact SRAM-like structure for volatile data storage, enabling fast read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM cell structure is used, then access speed is improved, but data volatility worsens
Solution Approach 1:
The patent combines SRAM and flash memory into a single hybrid memory cell, merging the fast access capability of SRAM with the non-volatile data retention of flash memory. The cell uses six transistors and two capacitors to implement both volatile storage (in capacitors) and non-volatile storage (in floating gate structures), allowing the same physical structure to provide both rapid access and data persistence without requiring separate memory components.
Solution Approach 2:
The hybrid memory cell performs multiple functions within a single device structure: it can operate as volatile memory for fast temporary storage, as non-volatile memory for persistent storage, and can maintain data across power cycles. The dual-capacitor design with floating gates enables the cell to function as both SRAM (when powered) and flash memory (when unpowered), eliminating the need for separate volatile and non-volatile memory components.
2Reliability
If flash memory is used, then non-volatile data storage is improved, but access speed worsens
Solution Approach 1:
The patent combines SRAM and flash memory into a single hybrid memory cell, merging the fast access capability of SRAM with the non-volatile data retention of flash memory. The cell uses six transistors and two capacitors to implement both volatile storage (in capacitors) and non-volatile storage (in floating gate structures), allowing the same physical structure to provide both rapid access and data persistence without requiring separate memory components.
Solution Approach 2:
The hybrid memory cell performs multiple functions within a single device structure: it can operate as volatile memory for fast temporary storage, as non-volatile memory for persistent storage, and can maintain data across power cycles. The dual-capacitor design with floating gates enables the cell to function as both SRAM (when powered) and flash memory (when unpowered), eliminating the need for separate volatile and non-volatile memory components.
3Reliability
If flash memory is used, then non-volatile data storage is improved, but power consumption worsens
Solution Approach 1:
The patent combines SRAM and flash memory into a single hybrid memory cell, merging the fast access capability of SRAM with the non-volatile data retention of flash memory. The cell uses six transistors and two capacitors to implement both volatile storage (in capacitors) and non-volatile storage (in floating gate structures), allowing the same physical structure to provide both rapid access and data persistence without requiring separate memory components.
Solution Approach 2:
The hybrid memory cell performs multiple functions within a single device structure: it can operate as volatile memory for fast temporary storage, as non-volatile memory for persistent storage, and can maintain data across power cycles. The dual-capacitor design with floating gates enables the cell to function as both SRAM (when powered) and flash memory (when unpowered), eliminating the need for separate volatile and non-volatile memory components.
4Quantity of substance
If conventional memory cells are used, then data storage is achieved, but device area increases
Solution Approach 1:
The patent combines SRAM and flash memory into a single hybrid memory cell, merging the fast access capability of SRAM with the non-volatile data retention of flash memory. The cell uses six transistors and two capacitors to implement both volatile storage (in capacitors) and non-volatile storage (in floating gate structures), allowing the same physical structure to provide both rapid access and data persistence without requiring separate memory components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact memory cell capable of storing both volatile and non-volatile data with fast access speeds and low power consumption, overcoming the limitations of existing technologies by maintaining data integrity even without a supply voltage and integrating well with CMOS.
Implementation Method 1
A memory cell design incorporating a resistance switching element that stores non-volatile data, allowing for quick access and low power consumption by leveraging leakage currents and resistive states
Data Source
Figure 1~2
Figure 3~5
Figure 6~7D
AI summary
The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply voltage (GND, VDD); a second transistor (104) coupled between a second storage node (108) and said first supply voltage, control terminals of the first and second transistors being coupled to the second and first storage nodes respectively; and a single resistance switching element (202), wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances (Rmin, Rmax), wherein said first storage node is coupled to a first access line (BL) via a third transistor (110, 810) connected to said first storage node, and said second storage node is coupled to a second access line (BLB) via a fourth transistor (112, 812) connected to said second storage node.