SRAM Write Assist Circuit With Hybrid-Stack Bitline Boost
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Solution Overview
Problem
Conventional write assist circuits in SRAM memory cells are inefficient due to their integration with existing circuit designs, leading to area penalties and reliability concerns, especially when operating at higher voltages, and they slow down write operations due to the RC time constant associated with the bitline.
Innovation Solution
A hybrid-stack write driver is integrated with a charge pump, featuring a two-stack device for primary bitline pull-down and an alternate three-stack path for write assist, which improves pull-down time and performance without disrupting existing circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write assist circuits are integrated with existing circuit designs, then area penalties occur and reliability concerns arise at higher voltages, but write assist functionality is provided
Solution Approach 1:
The write assist circuit is segmented from the main memory array and placed in a separate metallization layer. This allows the write assist functionality to be provided independently without integrating it directly with the memory cells, thereby improving reliability by isolating voltage-related stress and reducing device complexity through modular design.
Solution Approach 2:
The write assist circuit is moved to a different spatial dimension by placing it in a separate metallization layer above or below the memory array. This dimensional separation allows the write assist circuit to operate independently without interfering with the memory cell structure, resolving the contradiction between providing write assist functionality and avoiding area penalties and reliability concerns.
2Reliability
If the number of transistors in the bitline path is increased, then write assist capability is improved, but pull down time increases and write speed decreases
Solution Approach 1:
The write assist circuit uses a segmented transistor stack architecture with transistors arranged in multiple stages. This segmentation allows the write assist signal to be applied in a controlled manner through the stack, providing sufficient write assist capability while managing the total on-resistance to maintain acceptable pull-down time and write speed.
Solution Approach 2:
The write assist circuit changes the electrical parameters of the bitline path by dynamically controlling the resistance of individual transistor stages in the stack. By adjusting the conduction state of each stage independently, the circuit can provide strong write assist when needed while maintaining faster pull-down characteristics, thus resolving the contradiction between write assist capability and write speed.
3Productivity
If higher voltages are used for write operations, then write assist effectiveness is improved, but reliability concerns increase
Solution Approach 1:
The voltage for write operations is segmented across multiple transistor stages in the write assist circuit. Instead of applying high voltage directly to the bitline, the voltage is distributed and controlled through each stage of the transistor stack, allowing effective write operations while preventing excessive voltage stress on individual devices, thus maintaining reliability.
Solution Approach 2:
The write assist circuit introduces intermediary transistor stages between the voltage source and the bitline. These intermediary transistors control and regulate the voltage applied during write operations, enabling effective writing at controlled voltage levels while protecting the memory cells from reliability-damaging high voltage stress.
Data Source
AI summary
A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.