Dynamic Decode Circuit With Delayed Precharge Glitch Control
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Solution Overview
Problem
Dynamic decode circuits in dynamic logic face performance issues due to premature discharging of gates, leading to glitches and reduced efficiency, especially when cascading gates, as they rely on precharge states that cannot be restored until the next clock cycle.
Innovation Solution
The dynamic decode circuit is designed with a delayed precharge function that begins precharge a predetermined time after the evaluate period ends, and includes a special precharge circuit with a delayed evaluation clock signal to reduce the likelihood of unwanted glitches, allowing the output to remain active longer and improving performance by reducing transistor size and enhancing stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dynamic decode circuits use precharge states for evaluation, then the circuit can operate in dynamic logic mode with faster switching, but glitches occur due to premature discharging of gates before the next clock cycle
Solution Approach 1:
The patent applies preliminary action by precharging the decode circuit gates before the evaluate phase begins. The precharge transistor activates early in the clock cycle to charge all decode gates to a known high state, ensuring that when evaluation starts, all gates are ready to respond correctly to input signals without glitching from undefined or residual states.
Solution Approach 2:
The patent uses an intermediary precharge transistor that acts as a mediator between the power supply and the decode gates. This transistor controlled by the clock signal temporarily connects the power supply to the decode gates during the precharge phase, allowing controlled charging without direct connection that would cause uncontrolled discharge or glitches during evaluation.
2Productivity
If the decode circuit evaluates immediately when the word line goes high, then read performance improves, but the precharge state cannot be restored until the next clock cycle causing performance degradation
Solution Approach 1:
The patent implements periodic action by using a clocked precharge transistor that activates during a specific window within each clock cycle. The precharge occurs periodically at the beginning of each clock cycle before evaluation, creating a rhythmic pattern of precharge-evaluate-precharge that allows the circuit to maintain performance without waiting for the next full clock cycle to restore the precharge state.
3Quantity of substance
If transistor size is reduced to improve density, then more circuits can be integrated, but the circuit becomes more susceptible to glitches and noise
Solution Approach 1:
The patent applies preliminary anti-action by precharging the decode gates to a strong high state before evaluation begins. This preliminary charging creates a robust voltage level that is resistant to noise and glitches, allowing smaller transistors to be used without sacrificing noise immunity, as the precharged state provides a strong reference that prevents erroneous discharge.
Data Source
AI summary
A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.