Programmable Bypass Level Shifter for Dual-Voltage Memory Timing
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Solution Overview
Problem
In modern circuit design, the implementation of dual voltage rails for bitcell core and periphery circuitry often results in power savings limitations due to the need for level shifting, which can cause timing degradation and delay penalties in memory access and input pin setup times.
Innovation Solution
The implementation of level shifting circuitry with bypass switching circuitry allows for programmable bypass options, enabling high-speed level shifting across large voltage ranges by activating or deactivating the level shifting circuitry based on a bypass control signal, thereby reducing timing delays and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If level shifting circuitry is implemented to enable large range level shifting from low VDDPE to higher VDDCE domain, then voltage domain translation capability is improved, but timing delay and memory access time increase
Solution Approach 1:
The level shifting function is segmented into multiple stages rather than a single large-range level shifter. The bypass switching circuitry divides the signal path into different routing options, allowing the system to select between direct bypass (for speed) and level shifting paths (for voltage translation), thereby resolving the timing penalty while maintaining adaptability.
Solution Approach 2:
The bypass switching circuitry dynamically selects between bypass mode and level shifting mode based on operational requirements. This dynamic switching allows the system to adapt to different timing and voltage requirements, improving both speed performance and voltage domain translation capability as needed.
2Loss of energy
If level shifting is applied to all inputs inside memory, then power savings through VDDPE lowering is improved, but input pins setup time and memory access time degrade
Solution Approach 1:
Instead of applying level shifting uniformly to all inputs, the bypass switching circuitry enables selective application of level shifting only where voltage domain translation is required. Critical time-sensitive signals can bypass the level shifting circuitry, maintaining fast setup times while still enabling power savings through localized level shifting in non-critical paths.
Solution Approach 2:
The system dynamically configures which signals undergo level shifting versus bypass based on timing requirements and power optimization goals. This dynamic selection allows the system to achieve power savings by lowering VDDPE while maintaining acceptable timing performance for critical signals through the bypass path.
3Loss of time
If bypass switching circuitry is added to enable quick path for signals, then timing delay is reduced, but device complexity increases
Solution Approach 1:
The bypass switching circuitry is merged with the existing level shifting circuitry to form an integrated structure. The bypass switches are incorporated into the same circuit block as the level shifters, sharing common transistors and control logic, thereby reducing the overall complexity increase while providing the timing benefit of the bypass path.
Data Source
AI summary
Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.