Self-Clocked Write Bitline Drivers With Voltage Level Shifting
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Solution Overview
Problem
Conventional write driver circuits for memory arrays face challenges with controlling setup and hold times, leading to race conditions and power consumption issues, and require complex voltage scaling due to the use of tri-state drivers and single level shifters, which affect writability and power efficiency.
Innovation Solution
The implementation of voltage level shifted self-clocked tristated write bitline drivers using separate full voltage level shifters and CMOS circuits to manage data inputs across different voltage domains, eliminating the need for a write enable clock and reducing power consumption by allowing bitlines to float during inactive periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional tri-state drivers are used to drive write bitlines, then the bitlines can be floated during inactive periods to reduce leakage power, but setup and hold time control becomes difficult leading to race conditions
Solution Approach 1:
The write driver circuit uses self-clocked operation where the write data signals themselves control the timing of the bitline driving. The circuit automatically manages setup and hold requirements through its inherent feedback mechanism, eliminating the need for external clock control and preventing race conditions while maintaining the ability to float bitlines for power savings
2Ease of operation
If stacked transistors are used in tri-state drivers for driving and floating bitlines, then the drivers can control bitline states, but writability at low supply voltages is affected and larger sizing is required increasing area and dynamic power
Solution Approach 1:
The write driver is segmented into separate push-pull driving circuits for true and complement bitlines, with each circuit using independent transistor arrangements. This segmentation eliminates the need for stacked transistors, reducing the required transistor count from 4-6 per driver to 2-3 per driver, thereby reducing area while maintaining full driving capability
Solution Approach 2:
Instead of using stacked transistors in a conventional configuration, the invention inverts the approach by using parallel transistor arrangements with complementary switching. The pull-up and pull-down networks are reconfigured to operate independently, improving writability at low voltages without requiring larger device sizes
3Adaptability or versatility
If a single level shifter is used to translate voltage domains for write bitlines, then voltage translation is achieved, but the driver enters an unknown state during low phase or zero binary values that is difficult to recover from
Solution Approach 1:
The voltage level shifting function is segmented and integrated into separate push-pull driving circuits rather than using a single shared level shifter. Each bitline driver has its own level shifting capability, eliminating the unknown state problem that occurs in single level shifter configurations during low phase or zero binary values
Solution Approach 2:
The invention introduces clamping signals as intermediary elements that prevent the level shifter from entering unknown states. These clamping signals act as mediators between the voltage domains, ensuring stable operation during transitions and eliminating the recovery difficulties associated with conventional single level shifters
4Ease of operation
If conventional tri-state drivers are used with write enable clock, then driving and floating functions are achieved, but dynamic power is lost from unnecessary switching of static write bitlines
Solution Approach 1:
The write driver operates with periodic action only during active write cycles. The push-pull circuits are enabled only when write data is valid, and the bitlines are floated during inactive periods. This periodic operation eliminates unnecessary switching, reducing dynamic power consumption while maintaining full driving capability when needed
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2A
AI summary
Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.