Flip-Flop Input Selection Timing for Scan Hold-Time Violations
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Solution Overview
Problem
Sequential circuits face issues with scan hold-time violations and low voltage operation, particularly due to the lack of effective solutions that do not require additional delay circuits, which increase power consumption and area.
Innovation Solution
The proposed solution involves a flip-flop circuit design with a selection circuit, memory element, and clock circuit that generates earlier and later versions of the clock signal, allowing the selected input signal to be held stable during read operations, and includes a non-inverting enable circuit to prevent inadvertent copying of inverted signals, thereby reducing hold time requirements and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional delay circuits are used to prevent hold-time violations, then hold time adherence is improved, but power consumption and area increase
Solution Approach 1:
The patent extracts and eliminates the need for additional delay circuits by using the existing clock signal and its phases to control the selection circuit and memory element. The solution removes harmful unnecessary components while maintaining hold time adherence through clever use of clock phase timing.
Solution Approach 2:
The patent introduces the earlier version of the clock signal as an intermediary to control the selection circuit, and the later version to control the memory element. This intermediary clock mechanism coordinates the timing without requiring additional delay circuits, thus preventing hold-time violations without increasing power consumption or area.
2Reliability
If additional delay circuits are used to prevent hold-time violations, then hold time adherence is improved, but device area increases
Solution Approach 1:
The patent extracts and eliminates the need for additional delay circuits by using the existing clock signal and its phases to control the selection circuit and memory element. The solution removes harmful unnecessary components while maintaining hold time adherence through clever use of clock phase timing.
Solution Approach 2:
The patent makes the clock circuit multi-functional by using different phases of the same clock signal to control both the selection circuit and the memory element. This universal clock mechanism performs multiple timing functions without requiring separate delay circuits, thus reducing device area while maintaining reliability.
3Reliability
If the selection circuit is controlled to hold input signal stable, then hold time violations are reduced, but circuit complexity increases
Solution Approach 1:
The patent introduces the earlier version of the clock signal as an intermediary to control the selection circuit, and the later version to control the memory element. This intermediary clock mechanism coordinates the timing without requiring additional delay circuits, thus preventing hold-time violations without increasing power consumption or area.
Solution Approach 2:
The patent changes the timing parameters by using phased clock signals with specific time relationships. The earlier and later versions of the clock signal provide the necessary time separation to hold the input signal stable without requiring complex control logic, thus reducing circuit complexity while maintaining reliability.
4Reliability
If non-inverting enable circuit is added to prevent inadvertent copying, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent changes the timing parameters by using phased clock signals with specific time relationships. The earlier and later versions of the clock signal provide the necessary time separation to hold the input signal stable without requiring complex control logic, thus reducing circuit complexity while maintaining reliability.
Solution Approach 2:
The patent extracts and eliminates the need for additional delay circuits by using the existing clock signal and its phases to control the selection circuit and memory element. The solution removes harmful unnecessary components while maintaining hold time adherence through clever use of clock phase timing.
Data Source
AI summary
According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.