Asynchronous Clock Generation for Back-to-Back MRAM Access
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Solution Overview
Problem
Conventional magnetic memory devices require overhead operations like ACTIVATE and PRECHARGE for read and write operations, which can be inefficient, especially in embedded-MRAM applications where back-to-back operations are necessary without these overheads.
Innovation Solution
The implementation of asynchronous clock signals generated using edge-triggered delay cells to enable back-to-back access operations in magnetic memory devices with two magnetic tunnel junctions (MTJs) and two select devices per memory cell, allowing for direct reading and writing without the need for ACTIVATE or PRECHARGE commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional double data rate (DDR) memory access operations are used, then read and write operations can be performed with standard ACTIVATE and PRECHARGE commands, but overhead operations slow down back-to-back access operations
Solution Approach 1:
The patent extracts and eliminates the ACTIVATE and PRECHARGE overhead operations from the memory access sequence. By using asynchronous clock signals generated from edge-triggered delay cells, the system performs read and write operations directly without requiring these intermediate commands, thereby reducing access time and enabling faster back-to-back operations.
Solution Approach 2:
The patent implements dynamic clock signal generation using edge-triggered delay cells that create asynchronous clock phases. This dynamic approach allows the memory system to adapt clock timing for continuous back-to-back operations, eliminating the static timing constraints of conventional DDR memory that require ACTIVATE and PRECHARGE overhead.
2Reliability
If two magnetic tunnel junctions (MTJs) and two select devices are used per memory cell, then complementary state storage improves read-signal margin, but device complexity increases
Solution Approach 1:
The patent segments the memory cell into two distinct MTJs and two select devices, with each MTJ storing complementary states. This segmentation enables differential read operations where the voltage drops from both MTJs are compared, significantly improving read-signal margin while maintaining a structured and manageable cell architecture.
Solution Approach 2:
The patent applies local quality by giving each MTJ a specific function: one MTJ stores data in a high-resistance state while the other stores the complementary data in a low-resistance state. This localized functional differentiation within the memory cell enables enhanced signal detection through comparison, improving reliability without requiring complex external circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient and fast data access in embedded-MRAM applications by eliminating the overhead of ACTIVATE and PRECHARGE operations, improving read-signal margin and speed through complementary state storage in 2T2MTJ memory cells.
Implementation Method 1
The resistance in each MTJ can be varied based on the relative magnetic states of the magnetoresistive layers within the MTJ stack
Implementation Method 2
A dielectric tunnel barrier may be disposed in between the portions having the 'fixed' and 'free' magnetic states
Data Source
AI summary
The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a first memory cell, a first clock-generating circuit, and a second clock-generating circuit. The first clock-generating circuit is configured to provide a first output signal and a second output signal. The second clock-generating circuit is configured to provide a third output signal and a fourth output signal. The first output signal, the second output signal, the third output signal, and the fourth output signal are configured for controlling access operations for the first memory cell.