Adaptive DCO Slope Control for Supply-Droop Clock Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Clock generator circuits face instability due to noise on the power supply line, which can cause fluctuations in the system clock signal, leading to inefficiencies and potential chip failure, as existing compensation methods are slow and energy-inefficient.
Innovation Solution
An adaptive oscillator circuit that automatically adjusts its output clock frequency in response to noise on the power supply line by using a combination of delay lines and an edge detector to track voltage changes, ensuring sufficient time margins for sequential circuitry and preventing failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-step process is used to detect noise and slow down clock frequency, then clock signal stability is improved, but response speed deteriorates
Solution Approach 1:
The patent combines the noise detection function and clock frequency adjustment function into a single integrated circuit block. The detector directly controls the DCO without requiring separate notification and response steps, enabling simultaneous detection and response that resolves the speed-stability contradiction.
Solution Approach 2:
The patent implements a feedback mechanism where the detector monitors power supply noise and automatically adjusts the DCO frequency in real-time. This closed-loop feedback system enables rapid response to noise conditions without manual intervention, improving both response speed and clock stability.
2Reliability
If margins are added to power supply voltage to cover droop, then clock circuit timing reliability is improved, but power consumption increases
Solution Approach 1:
The patent uses a dynamically adjustable DCO whose frequency can be modified in real-time based on detected noise conditions. This dynamic adjustment eliminates the need for static voltage margins, allowing the system to maintain timing reliability only when necessary and reducing power consumption during normal operation.
Solution Approach 2:
The patent changes the operating parameters of the clock generator by adjusting the DCO frequency in response to power supply conditions. Instead of maintaining fixed voltage margins, the system adapts the clock frequency parameter to match actual power supply quality, reducing unnecessary power consumption while maintaining timing reliability.
Data Source
AI summary
An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.