Adaptive Frequency Divider Circuit for Low-Noise 10 GHz Clocks
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Solution Overview
Problem
Conventional RF synthesizer frequency divider circuits face challenges in high clock speeds exceeding 10 GHz, leading to increased far-off phase noise and power consumption due to fixed frequency divider circuitry and the need for additional resampling components to meet stringent timing requirements.
Innovation Solution
The implementation of a frequency divider circuit with an adjustable delay circuit regulated by sub-sampling feedback, utilizing a buffer, divider, and feedback circuit to reduce phase errors and power consumption, along with a ripple counter and multiplexer to provide a divided clock signal, effectively mitigating phase noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional fixed frequency divider circuitry is used to divide high frequency VCO output signals, then the divider can operate at high clock speeds, but far-off phase noise performance deteriorates and power consumption increases
Solution Approach 1:
The patent applies dynamics by making the divider circuit frequency-adaptive, allowing it to dynamically adjust its operation mode based on the input frequency. The circuit transitions from a static fixed-frequency design to a dynamic one that can optimize its performance characteristics across different frequency ranges, thereby reducing phase noise while maintaining high-speed operation capability
Solution Approach 2:
The patent changes key operating parameters of the divider circuit including phase advance adjustment and frequency-adaptive timing modification. By dynamically adjusting these parameters based on input frequency conditions, the circuit optimizes phase noise performance across different operating frequencies while maintaining high-speed division capability
2Manufacturing precision
If resampling latches or flip-flops are added to meet stringent timing requirements at 10 GHz, then timing specifications are satisfied, but power consumption increases
Solution Approach 1:
The patent modifies timing parameters dynamically based on input frequency. By adjusting phase advance and timing characteristics adaptively, the circuit meets stringent timing specifications at 10 GHz without requiring additional power-consuming resampling flip-flops, thus resolving the contradiction between timing precision and power consumption
3Adaptability or versatility
If the division ratio is increased to support both high and low frequency circuits, then system versatility is improved, but phase errors worsen at high input frequencies
Solution Approach 1:
The patent implements frequency-adaptive phase advance that dynamically adjusts based on input frequency and division ratio. This dynamic adjustment maintains phase accuracy across the full frequency range while supporting both high and low frequency circuits, resolving the contradiction between versatility and phase precision
Data Source
AI summary
Disclosed examples include frequency divider circuits to divide a high frequency first clock signal to generate an output clock signal at a lower frequency, including a delay circuit to provide a delayed clock signal, a divider circuit to provide a divided clock signal, a sub-sampling circuit to sub-sample the first clock signal with the divided clock signal, and a feedback circuit to set the delay value of the adjustable delay circuit according to the sub-sampled output signal.