A counter, delay circuit, and multiplexer enable 0.5-step clock division while maintaining 50% duty cycle and suppressing subharmonics.
Cascaded writable D flip-flops simplify image-sensor ADC counting, enabling CDS, lower power, smaller layout, and stable ADAF in HDR readout.
By filtering armature current ripple, this case derives DC motor speed and rotor position without Hall sensors or magnetic rings.
A strong-arm latch divides a single-phase clock into accurate differential half-frequency outputs while cutting power and easing timing alignment.
By filtering armature current ripple, this circuit derives DC motor speed and rotor position without Hall sensors or magnetic rings.
Grouped-bit reload logic lets an N-bit counter restart cleanly under clock glitches, reducing metastability and output frequency deviation.
Programmable counter-timer units generate complex peripheral pulse patterns without per-transition CPU control, cutting load and power use.
Digital sampling of unit-interval clock pulse widths detects phased clock error and adjusts delay paths to reduce SERDES jitter.
Sub-sampling feedback adjusts divider delay to cut phase noise and power in 10 GHz clock division without extra resampling latches.
Segmenting divisor bits lets an asynchronous divider sustain higher clock frequency and lower power by adding LSBs only on selected cycles.