Phased Clock Pulse-Width Correction for SERDES Jitter
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Solution Overview
Problem
Phased clock circuits, particularly in SERDES applications, face issues with deterministic jitter and error due to slight differences in phase-locked loops and manufacturing variance, which impact link performance at high data rates.
Innovation Solution
The implementation of a phased clock error handling system that converts phased input clock signals into unit interval clocks, digitally samples their pulse widths, and adjusts delays to correct for detected errors, allowing for error detection and correction across a wide error range with small resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple phased clocks are used to increase data rate, then productivity is improved, but reliability deteriorates due to deterministic jitter and quadrature error
Solution Approach 1:
The patent implements a feedback mechanism where the pulse width detector continuously monitors the pulse widths of phased clock signals and feeds this information back to the delay adjustment circuit. This closed-loop feedback enables real-time detection and correction of quadrature errors, maintaining reliable link performance while utilizing multiple phased clocks for high data rate transmission.
Solution Approach 2:
The system performs self-correction by automatically detecting pulse width variations and adjusting delays without external intervention. The delay adjustment circuit autonomously modifies the timing of phased clock signals based on detector feedback, enabling the system to self-correct deterministic jitter and maintain reliable operation at high data rates.
2Productivity
If phased clocks with slight differences are combined to achieve higher data rate, then productivity is improved, but manufacturing precision deteriorates due to phase-locked loop variations and manufacturing variance
Solution Approach 1:
The patent dynamically adjusts the delay parameter of phased clock signals based on detected pulse width variations. By changing the delay parameter in response to manufacturing variations and phase-locked loop differences, the system compensates for clock phase inaccuracies and maintains precise timing despite using multiple clocks with inherent manufacturing tolerances.
3Measurement precision
If digital sampling is used to detect pulse width differences, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog measurement circuits with digital sampling and counting mechanisms. Instead of using sophisticated analog pulse width measurement equipment, the system uses digital samplers and counters to accurately measure pulse widths by counting clock cycles, achieving high measurement precision while reducing circuit complexity.
4Reliability
If delay adjustment is implemented to correct pulse width differences, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a dynamic delay adjustment mechanism that adapts to varying pulse width errors in real-time. The delay adjustment circuit dynamically modifies the timing of phased clock signals based on continuous feedback from the pulse width detector, enabling reliable clock synchronization while maintaining flexibility to handle different error conditions without requiring overly complex fixed compensation circuits.
Data Source
AI summary
Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.