Writable D Flip-Flop Counter Layout for High-Speed Image ADC
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Solution Overview
Problem
Existing CMOS image sensors face challenges with complex circuit structures, high power consumption, and instability during auto-focus operations, particularly when implementing All-Direction Auto-Focus (ADAF) technology in Pixel-Gain High Dynamic Range (PGHDR) mode, which complicates the layout and increases parasitic capacitance and resistance.
Innovation Solution
A counter and analog-to-digital converter design with cascaded writable D flip-flops and CDS operations, allowing for reduced layout area, lower power consumption, and increased counting frequency, while enabling ADAF during High and Low Conversion Gain quantization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a reversible counter is used for CDS operations in SS ADC, then the counter can perform upward and downward counting for reset and exposure signal quantization, but the circuit structure becomes complex requiring two-to-one switches and buffers, increasing power consumption
Solution Approach 1:
The patent divides the counter into multiple independent counting units, each with its own D flip-flop. The first counting unit handles upward counting for reset signal quantization, while subsequent counting units handle downward counting for exposure signal quantization. This segmentation eliminates the need for complex two-to-one switches and buffers, reducing circuit complexity and power consumption while maintaining the ability to perform both upward and downward counting operations.
Solution Approach 2:
The patent implements dynamic control of counting direction by using a control signal that selectively enables or disables specific counting units based on the required operation mode. During reset signal quantization, the first counting unit is activated for upward counting; during exposure signal quantization, subsequent counting units are activated for downward counting. This dynamic switching approach replaces static reversible counter architecture, reducing the need for complex switching circuits.
2Reliability
If additional holding circuits are added to maintain stability during switching periods, then the stability of first quantization result is improved, but the layout becomes complicated and parasitic capacitance and resistance increase
Solution Approach 1:
The patent performs the first quantization of the reset signal completely before initiating the second quantization of the exposure signal. The counter is properly reset and stabilized after the first quantization operation, ensuring that the first quantization result is captured and stored before any switching to downward counting occurs. This preliminary completion of the first quantization eliminates the need for additional holding circuits during switching periods, as there is no overlapping operation that would require stability maintenance during transition.
3Use of energy by stationary object
If the counter structure is simplified to reduce power consumption, then power consumption decreases, but the maximum working frequency of the counter is limited
Solution Approach 1:
The patent segments the counter into multiple independent counting units with separate D flip-flops, allowing each unit to operate independently at optimal frequencies. This segmentation reduces the critical path delay compared to a single complex reversible counter, enabling higher maximum working frequencies while maintaining low power consumption through selective activation of only the necessary counting units for each operation.
Solution Approach 2:
Each counting unit in the patent is designed to be self-contained with its own D flip-flop and associated logic, allowing autonomous operation without requiring complex inter-unit coordination circuits. This self-service architecture reduces the overall circuit complexity and power consumption while maintaining high-speed operation, as each unit can be clocked independently at the maximum working frequency without being bottlenecked by complex switching mechanisms.
Data Source
AI summary
A counter, an analog-to-digital converter, and a method for reading out image signals; the counter comprises N cascaded counting units, each of which comprises a writable D flip-flop, which has a clock input, a data input, a Q output, a Q-bar output, a control input, and a write input; the clock input of the writable D flip-flop of each counting unit is connected to the Q-bar or Q output of the writable D flip-flop of a previous counting unit, except that the clock input of the writable D flip-flop of a first counting unit of the N cascaded counting units receives a clock signal; the Q-bar output of each writable D flip-flop is connected to the data input of the same writable D flip-flop, each Q output generates a counting result, each control input receives a control signal, and each write input receives a write signal.