Asynchronous Programmable Divider With Segmented Divisor Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Asynchronous counters in phase-locked loops have a maximum operation frequency that decreases and power consumption increases as the number of bits in the divisor increases due to ripple delay, limiting their performance in high-frequency applications.
Innovation Solution
A circuit design that includes an adder to generate a selectable divisor by combining most significant bits with an operand, a divider to divide the clock signal by this divisor, and additional logic to manage the division process, reducing the number of internal stages and power consumption while maintaining high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of bits in the divisor increases, then the division capability improves, but the maximum operation frequency decreases due to ripple delay
Solution Approach 1:
The divisor is segmented into most significant bits (MSBs) and least significant bits (LSBs). The MSBs are used to control the number of division iterations, while the LSBs are added to the MSBs only during specific iterations. This segmentation allows the divider to handle large division values without requiring a complete increase in the total bit width of the divisor register, thereby maintaining higher operating frequencies.
2Adaptability or versatility
If the number of bits in the divisor increases, then the division capability improves, but power consumption increases
Solution Approach 1:
The operand added to the MSBs is dynamically selected based on the iteration counter. During most iterations, the operand is zero, requiring no addition operation. Only during specific iterations (when the counter equals a threshold value) is the LSB operand added to the MSBs. This dynamic approach reduces the average power consumption compared to continuously adding all divisor bits.
Solution Approach 2:
The addition of the LSB operand to the MSBs occurs periodically rather than continuously. The logic circuit monitors the iteration counter and enables the addition operation only at specific periodic intervals (when counter equals the threshold). This periodic action reduces the overall power consumption while maintaining the required division capability.
3Speed
If the number of internal stages in the asynchronous divider is reduced, then power consumption and speed improve, but the division precision may be affected
Solution Approach 1:
The MSBs of the divisor are prepared in advance and held in a register before the division process begins. The iteration counter is also pre-configured with the threshold value. This preliminary preparation allows the divider to operate with fewer internal stages during the actual division iterations, improving speed, while ensuring that the complete divisor (MSBs + LSBs) is applied at the appropriate time to maintain precision.
Data Source
AI summary
A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.