N-Bit Counter Reload Logic for Glitch-Resistant Frequency Division
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional N-bit counters and frequency dividers are susceptible to glitches in the clock signal, leading to metastable states and improper reload signal timing, causing abnormal operation in phase-locked loops and frequency-divided clocks.
Innovation Solution
An N-bit counter and frequency divider design that includes an N-bit counting circuit, a reload signal generating circuit, and a reset circuit, where the reload signal changes based on a logical conjunction of K bits rather than all N bits, allowing timely reloading and resetting to prevent glitches from affecting the counting process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the reload signal generating circuit waits for all N bits to be at high level to trigger reload, then the counting accuracy is improved, but the circuit becomes susceptible to glitch causing metastable states and missed timing
Solution Approach 1:
The patent divides the N-bit count value into multiple groups of bits, where each group is monitored by a separate AND gate to generate intermediate signals. This segmentation allows the system to detect when sufficient bits have reached the high level without waiting for all N bits, thereby reducing susceptibility to glitch while maintaining counting accuracy.
Solution Approach 2:
The patent uses AND gates to preliminarily process the bit signals and generate intermediate reload signals before the final reload operation. This preliminary action enables the circuit to anticipate the completion of counting earlier, triggering the reload signal in advance while avoiding the metastable state caused by waiting for all N bits to stabilize.
2Measurement precision
If the circuit waits for all N bits to reach high level before reloading, then counting precision is improved, but the operation time increases by 2N cycles when glitch occurs
Solution Approach 1:
The circuit performs preliminary detection using AND gates on grouped bits to generate intermediate reload signals before all N bits are required to be high. This allows the reload operation to be triggered earlier, reducing the time loss that would otherwise occur when waiting for the full N-bit sequence to complete and restart.
Solution Approach 2:
The patent monitors only a subset of the N bits (K bits where K < N) using AND gates to generate the reload signal. This partial monitoring approach provides sufficient precision for reliable operation while significantly reducing the time penalty associated with waiting for all N bits to stabilize, especially under glitch conditions.
3Reliability
If the reload signal is triggered by all N bits being high, then the counting completeness is ensured, but the circuit reliability deteriorates under poor clock signal quality
Solution Approach 1:
By segmenting the N bits into groups and using AND gates to monitor each group, the circuit maintains counting completeness through the intermediate reload signal while reducing the impact of glitch. The segmented approach ensures that the reload is triggered based on sufficient bit transitions without requiring all N bits to be simultaneously stable.
Solution Approach 2:
The patent introduces intermediate reload signals generated by AND gates as mediators between the raw bit signals and the final reload operation. These intermediate signals filter out the harmful effects of glitch while preserving the essential counting information, thereby improving reliability under poor clock signal quality.
Data Source
AI summary
Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.