Strong-Arm Frequency Divider for Low-Power Differential Clocks
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Solution Overview
Problem
Frequency divider circuits face challenges in high-speed interfaces with high operating frequencies, particularly in managing power consumption and meeting timing constraints when dividing differential clock signals, as they often require differential flip-flops that double power consumption and struggle with signal alignment.
Innovation Solution
A frequency divider circuit utilizing a strong arm type latch circuit that alternately performs amplification and reset operations, generating differential clock signals of half the frequency of a single-phase clock signal without needing differential inputs, thereby avoiding the need for differential flip-flops and maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential flip-flops are used to divide the frequency of differential clock signals, then the frequency division function is achieved, but the power consumption is almost doubled
Solution Approach 1:
The frequency divider is segmented into two functional blocks: a strong arm latch circuit for frequency division and an inverter circuit for differential signal generation. This segmentation allows the frequency division function to be performed by a single-phase clock signal processing circuit, avoiding the need for power-consuming differential flip-flops, while the inverter circuit handles differential signal generation separately.
Solution Approach 2:
Instead of using differential flip-flops to directly divide differential clock signals (conventional approach), the invention inverts the approach by using a strong arm latch circuit that receives a single-phase clock signal, performs frequency division, and then uses an inverter circuit to generate the differential output signals. This inversion eliminates the need for differential input processing in the flip-flop stage.
2Reliability
If differential flip-flops are used to divide the frequency of differential clock signals, then the frequency division function is achieved, but it is not easy to meet timing constraints such as aligning the timing of the differential signals
Solution Approach 1:
The circuit is divided into a strong arm latch circuit for frequency division and a separate inverter circuit for differential signal generation. This segmentation allows independent optimization of timing characteristics in each block, making it easier to meet timing constraints compared to using differential flip-flops where timing alignment is inherently more difficult.
Solution Approach 2:
The inverter circuit acts as an intermediary between the strong arm latch circuit output and the final differential output. This intermediary stage allows for proper timing alignment and signal conditioning, ensuring that the differential output signals are properly synchronized without the timing alignment difficulties associated with differential flip-flops.
3Use of energy by moving object
If a strong arm type latch circuit is used to perform amplification and reset operations, then low power consumption is achieved, but the circuit must not reset nodes to which drains of input transistors are connected in the reset operation
Solution Approach 1:
The strong arm latch circuit dynamically switches between amplification mode and reset mode based on the clock signal phase. During the reset operation, the circuit selectively avoids resetting the nodes connected to the drains of input transistors, maintaining the dynamic behavior needed for low power consumption while preventing the harmful reset effect that would increase power consumption.
Solution Approach 2:
The reset operation applies different quality characteristics to different nodes in the circuit. Specifically, certain nodes (those connected to input transistor drains) are excluded from the reset operation, while other nodes are properly reset. This local differentiation of reset behavior maintains low power consumption by preserving the charge on critical nodes while still providing reset functionality where needed.
Data Source
AI summary
A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.