Adaptive Erase Control for Non-Volatile Memory Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Fowler-Nordheim erase procedures in non-volatile memory systems often result in over-erased memory cells, leading to increased column leakage and prolonged erase operation times, especially when dealing with memory blocks of varying sizes.
Innovation Solution
A memory controller adaptively determines whether to perform parallel or serial erase procedures based on block size and threshold voltage movement, sorting blocks into clusters and switching between parallel and serial FN erase methods within each cluster to optimize erase time and reduce over-erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel FN erase is performed on multiple blocks simultaneously, then erase operation speed is improved, but the number of over-erased bits increases leading to increased column leakage and longer soft program time
Solution Approach 1:
The patent dynamically adjusts the erase operation mode between parallel and serial based on real-time monitoring of threshold voltage distribution and over-erasure conditions. The system transitions from static parallel erase to adaptive hybrid erase, where the degree of parallelism is modulated according to actual memory cell states, thereby maintaining high speed while reducing over-erasure-induced leakage.
Solution Approach 2:
The patent changes operational parameters by monitoring threshold voltage movement and adjusting erase pulse characteristics dynamically. By detecting when threshold voltage exceeds target ranges, the system modifies subsequent erase pulse parameters (amplitude, duration) to prevent further over-erasure, thus reducing column leakage while maintaining efficient parallel operation.
2Reliability
If serial FN erase is performed on selected blocks, then over-erasure is reduced, but erase operation time is unnecessarily prolonged especially for small blocks
Solution Approach 1:
The patent segments the memory blocks into different groups based on their erase characteristics and requirements. Small blocks that require fast erase continue to use parallel mode, while blocks prone to over-erasure are switched to serial mode. This segmentation allows the system to optimize erase time for each block type independently, avoiding unnecessary time penalties for small blocks while maintaining over-erasure control where needed.
Solution Approach 2:
The patent implements dynamic mode switching between parallel and serial erase based on real-time conditions. The system monitors block characteristics and threshold voltage movement, then adaptively changes the erase mode for each block or group of blocks, ensuring that serial erase is applied only when necessary to prevent over-erasure, thereby minimizing time loss.
3Loss of time
If FN erase is always performed in parallel on all blocks, then total erase time is reduced, but soft program time increases due to increased over-erased bits
Solution Approach 1:
The patent implements feedback control by monitoring threshold voltage distribution during and after FN erase operations. The system detects the presence of over-erased bits through verify operations and uses this feedback to adjust subsequent erase and soft program parameters. This feedback mechanism allows the system to minimize over-erasure while maintaining efficient parallel operation, thereby reducing both total erase time and soft program time.
Solution Approach 2:
The patent employs periodic verify operations during the erase process to detect over-erased bits before they significantly impact performance. By periodically checking threshold voltage levels and interrupting parallel erase when over-erasure is detected, the system prevents excessive over-erasure that would require lengthy soft program correction, thus maintaining overall efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces memory device leakage and improves overall erase operation efficiency by dynamically adjusting erase procedures, ensuring faster FN erase times without incurring a time penalty for subsequent soft programming.
Implementation Method 1
For the erase operation, the pre-program procedure is followed by a Fowler-Nordheim (FN) erase procedure to lower the threshold voltages of the memory cells
Data Source
AI summary
A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.