Adaptive Erase Mode for Memory Wear Management
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Solution Overview
Problem
The wear of memory cells in rewritable non-volatile memory modules over time reduces their efficiency and can cause adverse effects on erase operations, leading to increased probability of reading erroneous data and longer programming times.
Innovation Solution
A configuration method for erase operations that adjusts the erase mode based on the wear degree of physical units in the memory module, using a memory controlling circuit unit to determine if the use state conforms to a default state and adjust the erase operation from one mode to another, thereby maintaining an appropriate threshold voltage distribution of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If continuous use of the rewritable non-volatile memory module increases storage capacity utilization, then the wear degree of memory cells worsens, leading to reduced erase operation efficiency and increased probability of reading erroneous data
Solution Approach 1:
The patent dynamically adjusts the erase operation mode based on the wear degree of the physical unit. The memory management circuit determines whether to apply a first erase mode or a second erase mode depending on the current wear state, making the erase operation adaptive rather than static. This dynamic adjustment resolves the contradiction by optimizing erase efficiency for each wear state.
Solution Approach 2:
The patent changes the erase operation parameters (mode) based on the wear degree of the memory cells. When the wear degree exceeds a threshold, the system switches from a first erase mode to a second erase mode, altering the operational parameters to compensate for wear and maintain reliable erase operations despite continuous use and capacity utilization.
2Duration of action of stationary object
If the wear degree of memory cells increases over time, then the threshold voltage distribution becomes inappropriate, causing increased programming time
Solution Approach 1:
The patent implements dynamic adjustment of erase operation modes based on wear degree monitoring. By continuously assessing the wear state and adapting the erase mode accordingly, the system maintains appropriate threshold voltage distribution throughout the memory cell's lifespan, preventing programming time increases that would otherwise occur with high wear.
Solution Approach 2:
The memory management circuit monitors the wear degree of physical units and uses this feedback to determine the appropriate erase mode. This closed-loop feedback mechanism ensures that erase operations are continuously optimized based on actual wear conditions, maintaining efficient programming times even as memory cells age and wear increases over time.
Data Source
AI summary
A configuration method of erase operation, a memory controlling circuit unit, and a memory storage device are provided. The method includes: determining whether a first use state of a first physical unit conforms to a first default state; and if the first use state conforms to the first default state, adjusting a first erase operation corresponding to the first physical unit from using a first mode to a second mode. Thereby, a threshold voltage distribution of memory cells in an erase state may be maintained in a proper range.