Read-Only Memories TRIZ Cases

A memory controller calculates common read offsets to group pages for efficient multi-plane access.

A process monitoring circuit generates stable output voltage insensitive to temperature variations.

Alternating programming of high and low states reduces threshold voltage changes caused by coupling between adjacent pages.

A semiconductor memory device suspends active write operations to execute concurrent read commands.

A continuous sensing mechanism monitors total string current during voltage ramping to determine optimal read points without predetermined levels.

A non-volatile memory programming method decodes sequential bits into error-corrected data using an intermediary module.

A storage device maps logical addresses to non-defective physical sectors during idle periods after shipment.

A memory controller shifts write operations across nonvolatile chips to reduce average current consumption.

Controller adjusts read thresholds based on neighbor states to restore margin without expanding array area.

Pre-computed LLR tables store reliability data to guide decoding, reducing latency in high-density solid state drives.

A flash memory control circuit charges and discharges the well voltage to reduce electron accumulation in unselected strings.

Read/write circuit isolates key bits in a dedicated latch to encrypt data, resolving vulnerability of exposed encryption keys.

A semiconductor fuse control unit manages terminal voltage states to prevent unintended electrical reconnection.

Segmenting memory into independent blocks reduces word line capacitance and mitigates hot electron injection in three-dimensional NAND flash.

A multiplexer uses shared high-voltage transistors and low-voltage control units to manage memory access lines.

A read voltage generating circuit produces a trim code before fuse word-line activation to stabilize gate-source voltage differences.

A nonvolatile semiconductor memory device applies distinct stepped write pass voltages to non-selected word lines.

Modulating supply voltage transmits opening keys to watch non-volatile memory, preventing transistor reliability degradation from high control voltages.

Block segmentation and string selection transistors reduce current leakage during three-dimensional array reads.

Auxiliary transistor limits saturation current in one-time programmable memory cells, reducing hot carrier degradation and improving programming reliability.

A voltage changing circuit generates a second voltage from a first voltage based on a difference between the second voltage and a reference voltage.

A column decoder selects bit lines based on leakage current magnitude to execute over erase correction in flash memory arrays.

Control logic applies a controlled potential gradient across word lines during the seeding phase to purge residue electrons from the memory cell channel.

Clamping circuits connect digit lines to fixed logic levels during refresh, enabling autonomous block erasure without external controller programming.

Controller classifies wordlines to apply single-pulse or multi-loop programming, reducing time while maintaining data reliability.

A memory device state machine switches between M-bit and N-bit per cell operating modes using prefix commands.

Substrate hole injection mechanism erases P-channel non-volatile memory cells using low operational voltage.

Vertical stacking of gate electrodes and mold insulation layers overcomes chip area limits while maintaining manufacturing efficiency.

Segmenting write phases into distinct threshold voltage ranges allows partial programming before full data input, reducing overall operation time.

Staggering charge pump activation during read operations stabilizes power source voltage and prevents circuit errors.

A nonvolatile memory device adjusts write voltage based on stored operation counts to ensure uniform layer characteristics.

Operation circuit adjusts program and erase loops based on cell current differences to control threshold voltages in semiconductor memory blocks.

A fuse circuit couples complementary transistors in series to block electrostatic discharge currents while enabling blowing current flow.

A CMOS non-volatile memory cell uses a shared floating gate with write and erase capacitors to store data via Fowler-Nordheim tunneling.

A non-volatile memory device selects between normal and data recover read schedulers to manage page buffer operations.

Reconstructs read addresses from selection signals to detect unauthorized data access via error injection attacks on memory cell selection lines.

Intensified voltage programming signals corrupt failing memory block data, ensuring irrecoverability while verifying destruction status.

Flash memory controller executes asynchronous multi-plane independent read operations across parallel planes using dedicated shift registers.

Integrating antifuse oxide layers with vertical transistor channels reduces manufacturing steps and machinery requirements.

Purified oxide semiconductor transistor eliminates leakage current to retain data without refresh operations.

Increasing channel potential of unselected memory strings reduces read disturb impact and enhances operational characteristics despite high integration density.

A memory control circuit adjusts erase operation modes based on physical unit wear states to maintain proper threshold voltage distributions.

A dynamic biasing comparator adjusts tail current to monitor supply voltage levels, resolving the speed-power tradeoff during glitches.

Dual verify reading operations using distinct voltages correct under-programmed cells, narrowing threshold voltage distribution profiles.

A memory device uses a mode register to select trim parameters from multiple fuse areas for specific performance modes.

A refresh module rewrites stored data to selected memory cells using high and low-level voltages on bit and word lines.

Grouping storage elements by neighbor state allows tailored pass voltages on unselected word lines, reducing program disturb and leakage.