Non-volatile Memory Read Scheduling for Coupled Cell Error Reduction
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Solution Overview
Problem
Current non-volatile memory devices face challenges in efficiently managing word line coupling, which leads to increased read errors due to widened threshold voltage distributions caused by parasitic capacitance coupling between adjacent memory cells, especially as memory density increases.
Innovation Solution
The implementation of a non-volatile memory device with a page buffer circuit and control logic that selects between normal and data recover read schedulers based on selection information from an external device, using N-bit latches to set logic states for page buffers corresponding to aggressor cells, and applying read voltages to differentiate coupled and uncoupled memory cells to reduce read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased to achieve higher storage capacity, then storage capacity is improved, but read errors increase due to word line coupling
Solution Approach 1:
The patent segments the read operation into two distinct phases: a first read operation for uncoupled memory cells and a second read operation for coupled memory cells. This segmentation allows the system to handle different cell types with appropriate read voltages, thereby reducing read errors while maintaining high memory density.
Solution Approach 2:
The patent changes the read voltage parameter based on the coupling state of memory cells. By applying a first read voltage to uncoupled cells and a second read voltage to coupled cells, the system optimizes the voltage parameter to minimize read errors in high-density memory configurations.
2Ease of operation
If normal read operation is used for all memory cells, then operation simplicity is maintained, but read errors increase for coupled memory cells
Solution Approach 1:
The patent introduces dynamic operation by selectively switching between different read operations based on the coupling state of memory cells. The control circuit dynamically determines whether to perform a first read operation or a second read operation, optimizing reliability without significantly complicating the overall operation.
Solution Approach 2:
The patent implements feedback mechanisms where the control circuit receives information about the coupling state of memory cells and adjusts the read operation accordingly. This feedback loop ensures that coupled cells receive appropriate read voltages to minimize errors while maintaining operational efficiency.
3Reliability
If data recover read operation is always used, then read error rate is reduced, but operation complexity and time increase
Solution Approach 1:
The patent applies partial action by performing the more complex second read operation only on coupled memory cells that require it, while using the simpler first read operation on uncoupled cells. This approach reduces the overall time penalty compared to always performing data recover read operations on all cells.
Solution Approach 2:
By segmenting the memory cell population into coupled and uncoupled groups, the patent applies different read operations to each segment. This segmentation prevents the unnecessary application of time-consuming data recover read operations to uncoupled cells, thereby reducing overall read operation time while maintaining high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces read errors by differentiating and managing coupled and uncoupled memory cells, improving data retrieval accuracy and reliability in high-density memory arrays.
Implementation Method 1
word line coupling, which leads to increased read errors due to widened threshold voltage distributions caused by parasitic capacitance coupling between adjacent memory cells
Data Source
AI summary
Disclosed is a non-volatile memory device which includes a memory cell array having memory cells arranged in rows and columns, a page buffer circuit configured to read data from the memory cell array, and a control logic and input/output interface block including a normal read scheduler controlling a normal read operation and a data recover read scheduler controlling a data recover read operation and configured to control the page buffer circuit at a read request. One of the normal read scheduler and the data recover read scheduler is selected according to selection information provided from an external device.