Multi-bit Write Strategy for NAND Flash Memory
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in the write operation process, particularly in reducing the time required for multi-bit write operations in three-dimensionally stacked NAND flash memory systems, where distinguishing between various threshold voltage levels is challenging, leading to increased operational complexity and time consumption.
Innovation Solution
The semiconductor memory device employs a multi-bit write operation strategy involving sequential commands to perform first, second, and third write operations, each targeting specific threshold voltage levels, allowing for partial write operations to be initiated before all data is input, and utilizing voltage programming and verifying operations to optimize write processes without prematurely increasing threshold voltages to unintended levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit write operations are performed in three-dimensionally stacked NAND flash memory, then storage capacity is improved, but write operation time increases and operational complexity increases
Solution Approach 1:
The patent segments the multi-bit write operation into multiple distinct phases: a first write operation for lower bits and a second write operation for upper bits. Each phase targets specific threshold voltage ranges, allowing parallel processing and optimization of each segment independently, thereby reducing overall write time while maintaining high storage capacity
Solution Approach 2:
The patent performs preliminary actions by conducting the first write operation for lower bits before completing data input for all bits. This allows the system to start programming earlier and use verification operations to determine when subsequent write operations can begin, overlapping data input with programming operations to reduce total write time
2Quantity of substance
If multi-bit write operations are performed in three-dimensionally stacked NAND flash memory, then storage capacity is improved, but operational complexity increases
Solution Approach 1:
The patent divides the complex multi-bit write operation into clearly defined segments with distinct objectives: the first write operation handles lower bits with specific threshold voltage targets, while the second write operation handles upper bits. This segmentation simplifies control logic by providing clear boundaries and verification points, reducing operational complexity despite maintaining high storage capacity
Solution Approach 2:
The patent implements feedback mechanisms through verification operations that monitor threshold voltage levels during write operations. These verification results provide feedback to determine when to transition between write phases and when data input is complete, automating complex control decisions and reducing operational complexity through intelligent process management
3Reliability
If threshold voltage levels are increased during write operations, then data is written to memory cells, but unintended threshold voltage increases occur leading to errors
Solution Approach 1:
The patent segments the threshold voltage programming into distinct ranges for different write operations. The first write operation targets lower threshold voltage ranges for lower bits, while the second write operation targets higher threshold voltage ranges for upper bits. This segmentation prevents unintended voltage increases by confining each programming operation to its specific voltage window, ensuring both data accuracy and precise voltage control
Solution Approach 2:
The patent dynamically changes programming parameters including voltage levels and pulse widths based on the current write phase and verification results. By adjusting these parameters adaptively, the system achieves precise control over threshold voltage increases, preventing unintended changes while ensuring reliable data writing across multiple bits
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells, and a control circuit configured perform a multi-bit write operation on the memory cells in response to sequentially received commands including a first command and a second command, which is received after the first command, the first command including first bits to be written respectively in the memory cells and the second command including second bits to be written respectively in the memory cells. The multi-bit write operation includes at least a first write operation including at least one program operation that is initiated after receipt of the first command and prior to the receipt of the second command, and a second write operation that is initiated after receipt of the second command.