Memory Device State Machine for Mixed Bit-Per-Cell Modes
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Solution Overview
Problem
Existing memory devices face challenges in efficiently operating with different numbers of bits per cell on different word lines, as current state machines are typically configured to assume a uniform number of bits per cell, leading to inefficiencies in mixed mode blocks where varying bit densities are required.
Innovation Solution
The memory device is configured with parameters for multiple operating modes, including M-bit and N-bit per cell modes, which are stored in ROM and loaded into registers upon power-on, allowing the state machine to easily switch between modes without requiring external controller intervention, using prefix commands to specify the operating mode and operation type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the state machine is configured to assume a uniform number of bits per cell, then the device complexity is reduced and operation is simplified, but the adaptability to mixed mode blocks with varying bit densities is worsened
Solution Approach 1:
The state machine is designed to dynamically switch between different bit-per-cell modes (M-bit and N-bit) based on prefix commands received during operation. This dynamic reconfiguration capability allows the same state machine to adapt to varying bit densities across different word lines without requiring multiple dedicated state machines, thus resolving the contradiction between simplified operation and mixed mode adaptability.
Solution Approach 2:
The invention changes the operational parameters of the state machine by loading different sets of parameters from ROM into registers based on the detected mode. When an M-bit mode prefix command is received, M-bit parameters are loaded; when an N-bit mode prefix command is received, N-bit parameters are loaded. This parameter switching mechanism enables the state machine to handle both uniform and mixed mode blocks efficiently.
2Adaptability or versatility
If parameters for multiple operating modes are stored in ROM and loaded into registers, then the adaptability to different bit densities is improved, but the device complexity increases
Solution Approach 1:
All possible parameter sets for different operating modes (M-bit and N-bit modes for program, read, and erase operations) are pre-stored in ROM during manufacturing. This preliminary preparation eliminates the need for dynamic parameter generation or external parameter transmission during operation, reducing the actual runtime complexity despite the presence of multiple parameter sets.
Solution Approach 2:
A single set of registers is designed to universally hold parameters for any operating mode. The same register structure and loading mechanism handle both M-bit and N-bit mode parameters, as well as all operation types (program, read, erase). This universal parameter storage approach avoids duplicating hardware structures for each mode, thereby limiting the increase in device complexity.
3Ease of operation
If prefix commands are used to specify operating mode, then the ease of operation is improved and external controller intervention is reduced, but the device complexity increases
Solution Approach 1:
The state machine itself performs the mode detection and parameter selection based on prefix commands embedded in the command sequence. Instead of requiring an external controller to analyze the command and determine the appropriate parameters, the memory device autonomously parses the prefix command, identifies the intended mode (M-bit or N-bit), and loads the corresponding parameters from ROM. This self-service approach simplifies external controller operation while keeping the command parsing logic integrated within the existing state machine framework.
Data Source
AI summary
Techniques are described for configuring a memory device with parameters for multiple operating modes including M-bit per cell and N-bit per cell operating modes. The parameters can be stored in ROM storage locations of the memory device and loaded into registers when powering on the memory device. The parameters can be accessed by a state machine based on command sequences receive from a controller. The command sequences can include one or more prefix commands which specify the operating mode, e.g., the number of bits per cell, commands which specify a type of an operation, and an address of memory cells on which the operation is to be performed. The state machine can easily switch between accessing parameters for different modes without the controller including the parameters in the command sequences.