Memory Address Reconstruction for Error Injection Detection
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Solution Overview
Problem
Integrated circuits, particularly those with non-volatile memories like ROM, EEPROM, and FLASH, are vulnerable to attacks through error injection, which alter memory cell selection signals, making it difficult to detect unauthorized data access without changing the memory content.
Innovation Solution
Implementing an address reconstruction method that compares the original and reconstructed addresses in real-time during data reading, using switches to bias logic states and convert selection signals, to verify the integrity of the address and detect errors in memory cell selection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification of memory content is performed to detect integrity defects, then detection of not valid data is improved, but detection of attacks that do not change memory content but cause wrong data reading is not achieved
Solution Approach 1:
The patent introduces an intermediary verification mechanism that reconstructs the address from selection signals and compares it with the original address. This intermediary address reconstruction process acts as a mediator to detect attacks that directly manipulate selection signals without altering memory content, thereby solving the detection gap in conventional verification methods.
Solution Approach 2:
The patent implements a feedback mechanism where the reconstructed address is continuously compared with the original address during memory operations. This feedback loop provides real-time detection of address alteration attacks, enabling the system to identify and respond to security threats that conventional one-time verification methods cannot detect.
2Reliability
If address reconstruction is performed in real-time during data reading, then detection of selection signal errors is improved, but additional circuit complexity and processing time are introduced
Solution Approach 1:
The patent designs the address reconstruction circuit to perform multiple functions: it reconstructs addresses from selection signals, compares them with original addresses, and provides error detection. This multi-functional approach reduces the need for separate verification circuits, thereby mitigating the increase in device complexity while maintaining enhanced reliability.
Solution Approach 2:
The patent merges the address verification function with the existing memory read operation by performing address reconstruction and comparison during the normal data reading process. This integration allows the verification mechanism to operate without requiring separate processing cycles, thereby reducing the impact on processing time while improving security.
3Object-affected harmful factors
If error injection attacks are applied to selection signals, then unauthorized data access is enabled, but the memory content itself remains unchanged making detection difficult
Solution Approach 1:
The patent performs preliminary address reconstruction and verification before the actual memory data is read and processed. By verifying the address integrity in advance, the system can detect error injection attacks on selection signals before they result in unauthorized data access, preventing the loss of information security rather than detecting it after the fact.
Solution Approach 2:
The patent implements preliminary anti-action by proactively verifying address integrity through reconstruction and comparison before memory operations proceed. This preemptive measure counteracts the effect of error injection attacks by detecting and blocking unauthorized access attempts before they can compromise data integrity, thereby preventing the harmful effect rather than merely responding to it.
Data Source
AI summary
A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.