LLR Tables for SSD Error Correction Latency
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Solution Overview
Problem
Current SSD devices, particularly those using MLC and TLC technologies, face limitations in error correction capabilities due to hard decoding's limitations and the high computational effort required for soft decoding, leading to increased latency and read access times as bit density per memory cell increases.
Innovation Solution
The implementation of improved LLR tables in SSD devices, which reduces the need for soft decoding by associating error information with symbol combinations, allowing for more efficient error correction and potentially avoiding soft decoding altogether, thereby enhancing error correction capabilities and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft decoding is used to improve error correction capabilities, then reliability is improved, but latency and read access time increase
Solution Approach 1:
The patent pre-calculates and stores LLR values for all possible read outcomes in lookup tables during device manufacturing or initialization. When reading data, the controller simply retrieves pre-computed LLR values from tables based on the actual read outcome, rather than performing complex soft decoding calculations in real-time. This preliminary preparation eliminates computational latency during actual read operations while maintaining soft decoding error correction capabilities.
Solution Approach 2:
The patent creates simplified copies of the soft decoding process by pre-computing LLR values and storing them in lookup tables. Instead of executing the full soft decoding algorithm during read operations, the system uses these table copies to provide LLR values directly to the decoder. This copying approach maintains the essential error correction functionality while dramatically reducing computational complexity and latency.
2Productivity
If bit density per memory cell is increased to improve storage capacity, then productivity is improved, but the need for soft decoding increases leading to higher latency
Solution Approach 1:
The patent addresses high-density memory challenges by pre-computing LLR values specific to the particular memory device's threshold voltage distributions during initialization. These device-specific LLR tables are stored in lookup memory, allowing the system to handle the increased error rates from high-density cells without incurring soft decoding latency during actual read operations. The preliminary characterization of each device enables optimized LLR values tailored to its specific performance characteristics.
3Productivity
If hard decoding is used to reduce computational effort, then productivity is improved, but error correction capability is limited
Solution Approach 1:
The patent introduces LLR lookup tables as an intermediary between the read operation and the decoder. These tables provide pre-computed reliability information (LLR values) that guide the decoding process. The hard decoder uses these LLR values to prioritize which bits to correct first, effectively combining the speed of hard decoding with the error correction intelligence of soft decoding. This intermediary layer enables the system to achieve soft decoding performance with hard decoding speed.
Data Source
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Figure 2A
AI summary
A solid state drive is proposed. The solid state drive comprises a plurality of memory cells each one programmable with a threshold voltage among a plurality of threshold voltages; each threshold voltage is associated with a respective bit pattern among a plurality of bit patterns and is variable over the plurality of memory cells thereby defining a respective threshold voltage distribution. Each pair of adjacent bit patterns can be discriminated, during a read operation, by a respective first reference voltage between the threshold voltages associated with the pair of adjacent bit patterns. The solid state drive also comprises a controller for storing a plurality of LLR tables; for each bit pattern combination comprising first, second and third bit patterns respectively associated with the first reference voltage, a second reference voltage higher than the first reference voltage, and a third reference voltage lower than the first reference voltage, each LLR table has an error information when that bit pattern combination is associated with respective threshold voltages that, based on the threshold voltage distributions, are inconsistent with each other, or a LLR value indicative of an outcome bit pattern and of an indication of reliability of the outcome bit pattern otherwise.