CMOS Non-Volatile Memory Cell With Shared Floating Gate
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Solution Overview
Problem
Conventional non-volatile memory systems require large layout areas, are not reprogrammable, and consume excessive power due to complex fabrication processes and lack of margin read operations, leading to low reliability and high power consumption.
Innovation Solution
A reprogrammable non-volatile memory cell using a conventional CMOS process with a flip-flop circuit that shares a floating gate with write and erase capacitors, implementing Fowler-Nordheim tunneling for charge induction and minimizing power consumption by eliminating current paths during read operations, along with a current injection circuit for margin read testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional differential floating gate non-volatile memory circuit is used, then non-volatile storage is achieved, but the layout area becomes large and circuit complexity increases
Solution Approach 1:
The patent combines the storage function and flip-flop circuit function into a single integrated structure. The floating gate is shared between the write capacitor and erase capacitor, and the same floating gate serves both storage and flip-flop state representation purposes. This merging eliminates the need for separate storage cells and flip-flop circuits, significantly reducing layout area while maintaining non-volatile storage capability.
Solution Approach 2:
The floating gate structure performs multiple functions simultaneously: it stores data bits, maintains flip-flop state, and enables both program and erase operations. The differential configuration of floating gates (FG0 and FG1) allows the same structure to represent binary data while providing margin read capability for reliability testing, making the circuit universally functional across multiple operations.
2Reliability
If conventional non-volatile memory circuit with multiple current branches is used, then program and erase operations are enabled, but power consumption increases
Solution Approach 1:
The patent employs periodic control of current branches through timed operation sequences. During program operations, only the write capacitor current branch is activated; during erase operations, only the erase capacitor current branch is activated. The flip-flop circuit uses periodic clock signals to control state transitions. This periodic activation of current branches ensures program and erase capability while minimizing simultaneous current paths and reducing overall power consumption.
3Device complexity
If conventional non-volatile memory without margin read operation is used, then circuit simplicity is maintained, but reliability testing capability is lost
Solution Approach 1:
The differential floating gate structure serves dual purposes: it stores data bits for normal operation and provides margin read capability for reliability testing. By monitoring the voltage levels on the differential floating gates (FG0 and FG1), the circuit can perform margin reads to test whether stored charges are above or below threshold levels, enabling reliability assessment without adding separate test circuitry.
4Adaptability or versatility
If Fowler-Nordheim tunneling is used for charge induction, then reprogrammability is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes Fowler-Nordheim tunneling by changing the electric field parameter across the oxide layer. By applying high voltage to the control gates, strong electric fields are induced that enable electron tunneling through the oxide to the floating gate. This parameter-based approach (controlling electric field strength through voltage) achieves reprogrammability without requiring changes to the physical manufacturing process, allowing standard CMOS fabrication to be used.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact, reprogrammable, and low-power memory cell with improved reliability through efficient charge management and margin read functionality, reducing layout area and power consumption while maintaining data integrity.
Implementation Method 1
An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate.
Implementation Method 2
A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate.
Data Source
AI summary
A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.