Semiconductor Memory Block Uniformity via Position-Dependent Control

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Solution Overview

Problem

Semiconductor devices with memory blocks face challenges in achieving uniform electrical characteristics due to varying characteristics across different memory blocks, leading to inconsistent operating conditions and reduced operational reliability.

Innovation Solution

A semiconductor device with a memory array and operation circuit that adjusts program and erase loop operations based on the difference between the cell current value of a selected memory block and a reference cell current value, controlling threshold voltages and verify operations to ensure uniformity across memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If memory blocks are arranged in line with varying characteristics, then device complexity is reduced, but electrical characteristics become non-uniform

Engineering Contradiction:
Improvememory block arrangementVSAvoidelectrical characteristics uniformity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by setting different operating conditions for different memory blocks based on their position. Specifically, memory blocks are divided into first memory blocks and second memory blocks, with different program/erase voltages or different numbers of program/erase loops applied to each group, compensating for position-dependent characteristic variations and achieving uniform electrical characteristics across all blocks.

Inventive Principle:
Principle #3Local quality

2Ease of operation

If operating conditions are set uniformly for all memory blocks, then ease of operation is improved, but electrical characteristics become inconsistent

Engineering Contradiction:
Improveoperating condition settingVSAvoidelectrical characteristics consistency
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent implements local quality by establishing position-dependent operating conditions. The controller identifies whether each memory block belongs to the first or second group based on its position, and applies tailored program/erase voltages or loop counts to each group, ensuring consistent electrical characteristics while maintaining automated operation through position-based classification.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies parameter changes by modifying operating parameters (program voltage, erase voltage, or number of loops) based on memory block position. This allows the system to adapt operating conditions to compensate for physical variations, achieving uniform electrical characteristics across different block positions without manual intervention.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If position-dependent operating conditions are applied, then electrical characteristics uniformity is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical characteristics uniformityVSAvoidoperating condition control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing memory blocks into distinct groups (first memory blocks and second memory blocks) based on their positions. This segmentation simplifies the control logic by creating discrete categories with predefined operating conditions, making the position-dependent control more manageable while still achieving uniform electrical characteristics across all blocks.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9627078B2Semiconductor device and operating method thereof
Publication Date: 2017.04.18 SK HYNIX INC
  • US9627078B2 patent drawing
  • US9627078B2 patent drawing
  • US9627078B2 patent drawing

AI summary

A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.