Secure Memory Read/Write Circuit Key Latch Encryption

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Solution Overview

Problem

Existing memory systems lack effective security measures to protect critical data from unauthorized access, as the encryption keys themselves are not adequately secured, making them vulnerable to attacks.

Innovation Solution

A memory system with a read/write circuit that includes a latch to store key bits and an encryption circuit to encrypt and decrypt data using these key bits, ensuring that only encrypted data is stored and retrieved, with the key bits being managed to prevent unauthorized access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is encrypted using a key stored in the memory system, then data security is improved, but the key itself becomes a vulnerability point for unauthorized access

Engineering Contradiction:
Improvedata securityVSAvoidkey accessibility vulnerability
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the key from the main memory array and stores it in a separate, dedicated key storage location within the read/write circuit. This physical separation isolates the key from the data storage area, creating a distinct security zone that is harder to access unauthorizedly while maintaining the encryption function.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a specialized key management circuit as an intermediary between the key storage and the encryption/decryption operations. This intermediary circuit controls key access tightly, allowing the key to be used for encryption purposes while preventing direct access to the key bits themselves, thus mediating between security requirements and functional needs.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a latch is added to store key bits in the read/write circuit, then key security is improved, but the circuit complexity increases

Engineering Contradiction:
Improvekey securityVSAvoidread/write circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the key storage latch with the existing read/write circuit structure, integrating the key management functionality into the data path rather than creating a completely separate key management subsystem. This integration reduces overall system complexity while maintaining security, as the latch shares control logic and physical proximity with the data processing elements.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The read/write circuit is designed to perform multiple functions: normal data read/write operations, key storage, and encryption/decryption. By making the read/write circuit universal and multi-functional, the patent avoids adding dedicated separate circuits for each function, thereby reducing overall complexity while achieving enhanced security through the integrated key latch.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If encryption operations are performed for every data write, then data protection is improved, but the operation time increases

Engineering Contradiction:
Improvedata protectionVSAvoidwrite operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs encryption operations in advance during the write process, so that when data is read back, decryption is not needed. By encrypting data before it is stored in the memory array, the system ensures protection without adding time to read operations, as the encryption is completed as part of the write sequence rather than being added to both read and write paths.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11978530B2Secure memory
Publication Date: 2024.05.07 STMICROELECTRONICS FRANCE
  • US11978530B2 patent drawing
  • US11978530B2 patent drawing
  • US11978530B2 patent drawing

AI summary

A memory includes memory cells arranged in rows and in columns, with at least one bit line for each column being coupled to the memory cells of the column. A read/write circuit is coupled to the bit lines and is configured to receive, for each column, a binary datum to be stored in one of the memory cells of the column. The read/write circuit includes, for each column, a latch configured to store a bit of a key, and an encryption circuit configured to encrypt the received binary datum with the bit of the key to provide encrypted binary datum. The read/write circuit controls the bit line to thereby store the encrypted binary datum.