Flash Memory Charge Pump Timing Control
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Solution Overview
Problem
The peak current during read operations in semiconductor memory devices, particularly in NAND type flash memory, causes a drop in the power source voltage due to high current consumption by the charge pump circuit, leading to unstable circuit operations and potential errors.
Innovation Solution
A semiconductor memory device with a controller that selectively activates multiple charge pump circuits at different timings during the read operation, such as in response to rising and falling edges of a clock signal, to distribute the current consumption and reduce peak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple charge pump circuits are activated simultaneously to generate high voltages for read operations, then the required voltages are supplied, but the peak current increases causing power source voltage drop
Solution Approach 1:
The patent applies periodic action by activating charge pump circuits at different time periods during the read operation. Specifically, the bit line precharge pump circuit is activated during the bit line precharge period, while the sense amplifier pump circuit is activated during the sense period, avoiding simultaneous activation and thereby reducing peak current
Solution Approach 2:
The patent segments the charge pump activation into multiple independent phases. The read operation is divided into distinct periods (bit line precharge period, sense period, etc.), and different charge pump circuits are activated in each period based on the specific voltage requirements, preventing concurrent high current draw
2Productivity
If charge pump circuits are activated to generate pass voltage and drive voltage, then read operations can proceed, but circuit stability deteriorates due to voltage drop
Solution Approach 1:
The patent implements periodic action by scheduling charge pump activations according to the read operation timeline. The bit line precharge pump operates during the precharge period, and the sense amplifier pump operates during the sense period, ensuring voltage supply matches operational needs without causing instability
Solution Approach 2:
The patent applies preliminary action by activating the bit line precharge pump circuit before the sense amplifier pump circuit. The bit line precharge occurs first to prepare the bit lines, and only after this preliminary step is complete does the sense amplifier operation begin, ensuring proper sequencing and stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the peak current during read operations, stabilizing the power source voltage and minimizing errors by controlling the activation timing of charge pump circuits.
Implementation Method 1
a voltage generation circuit that includes a charge pump circuit, a level shifter, or the like for boosting the power source voltage supplied from the outside to a desired voltage
Data Source
AI summary
A semiconductor memory device for reducing the peak current during the read operation is provided. A flash memory of the disclosure includes a memory cell array; a plurality of charge pump circuits; and a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.