Staircase Common Source Line for 3D Memory Integration
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Solution Overview
Problem
The degree of integration of two-dimensional (2D) memory devices is limited due to the need for expensive equipment for fine pattern formation and the limited area of a chip die.
Innovation Solution
An integrated circuit device with a cell array structure featuring a gate stack with alternately stacked gate electrodes and mold insulation layers, a channel structure with a channel layer and gate insulation layer, and a common source line structure with a staircase sidewall, which increases the degree of integration while maintaining efficient manufacturing and good operation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattern formation technology is used to increase the degree of integration of 2D memory devices, then the degree of integration is improved, but expensive equipment is needed
Solution Approach 1:
The patent transitions from two-dimensional memory device layout to a three-dimensional structure by stacking gate electrodes and mold insulation layers vertically to form a gate stack. This vertical stacking enables higher integration density without requiring advanced fine pattern formation technology, thereby reducing manufacturing costs while increasing the quantity of memory cells per chip.
2Quantity of substance
If the area of chip die is increased to improve degree of integration, then the degree of integration is improved, but the chip die area is limited
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple gate electrodes and mold insulation layers to form a three-dimensional gate stack structure. This approach increases the number of memory cells within the same chip die area by exploiting vertical space, thereby improving integration density without expanding the horizontal chip footprint.
Solution Approach 2:
The gate electrodes and mold insulation layers are nested alternately in the vertical direction to form a compact gate stack. This nested arrangement maximizes the use of vertical space within the chip die, allowing more memory cells to be packed into a limited area by organizing components in a hierarchical stacked configuration.
3Ease of manufacture
If traditional 2D memory device structure is used, then manufacturing process is simple, but the degree of integration is limited
Solution Approach 1:
The patent introduces vertical stacking of gate electrodes and mold insulation layers to create a three-dimensional gate stack structure. This dimensional transition enables higher integration density while maintaining compatibility with existing manufacturing processes, as the stacked structure can be formed using standard deposition and etching techniques without requiring complex fine pattern formation equipment.
Data Source
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AI summary
A cell array structure of an integrated circuit device includes a gate stack including gate electrodes and mold insulation layers, which extend in a horizontal direction and are alternately stacked in a vertical direction, a channel structure extending in the vertical direction in the gate stack including a channel layer and a gate insulation layer conformally covering the channel layer, the gate stack and gate insulation layer exposing a portion of an upper surface of the channel layer, an insulation pattern layer disposed on the gate stack, and the gate insulation layer and exposing the portion of the upper surface of the channel layer, and a common source line structure contacting the gate insulation layer, the insulation pattern layer, and the upper surface of the channel layer, wherein a sidewall of the common source line structure disposed in the gate stack has a staircase shape.