OTP Memory Cell Auxiliary Transistor for Hot Carrier Degradation
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Solution Overview
Problem
The reliability of memory cells in OTP integrated circuits is compromised due to stress on the gate oxide of access transistors during programming, particularly at 65 nanometers and below, leading to hot carrier degradation and difficulty in detecting the exact instant of dielectric impairment, which affects programming duration and cell performance.
Innovation Solution
Incorporating an auxiliary circuit with a transistor that has a lower saturation current than the access transistor, allowing for controlled programming and precise detection of dielectric degradation through voltage variations, and using cascode arrangements to enhance reliability and current precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access transistors with significant channel lengths are used to reduce strong current, then hot carrier degradation is reduced, but the surface area of the memory cell increases
Solution Approach 1:
The access transistor is divided into two separate transistors: a first access transistor for controlling word line access and a second access transistor for controlling bit line access. This segmentation allows each transistor to have optimized channel dimensions, reducing the need for long channel lengths while maintaining reliability through the distributed architecture.
Solution Approach 2:
A fuse element is introduced as an intermediary component between the two access transistors. This fuse element acts as a current limiter and protection mechanism, allowing the access transistors to operate with shorter channel lengths without suffering from excessive current and hot carrier degradation.
2Reliability
If programming voltage is reduced to improve reliability, then hot carrier degradation decreases, but programming duration increases
Solution Approach 1:
The programming voltage is dynamically adjusted during the programming process. The voltage starts at a higher level to quickly approach the dielectric breakdown point, then transitions to a lower sustained level to complete the programming without excessive hot carrier generation. This dynamic voltage control optimizes both speed and reliability.
Solution Approach 2:
The programming process uses periodic voltage pulses rather than a continuous DC voltage. These pulsed programming operations allow the dielectric to be stressed intermittently, achieving breakdown more efficiently while reducing the cumulative hot carrier stress on the access transistors.
3Reliability
If sufficiently long programming duration is fixed to ensure programming completion, then programming reliability increases, but the detection precision of actual programming instant decreases
Solution Approach 1:
A detection circuit continuously monitors the state of the dielectric during programming and provides feedback signals. When the dielectric breakdown is detected, the circuit generates a feedback signal that immediately terminates the programming process. This feedback mechanism enables precise detection of the programming instant while ensuring complete programming through continuous monitoring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of access transistors during programming, allows for more precise detection of programming completion, and optimizes the programming duration by reducing the drain/source voltage, thereby enhancing the overall performance of OTP memory cells.
Implementation Method 1
an auxiliary transistor electrically coupled between the first electrode and the first power supply terminal, able to be controlled on its auxiliary control electrode in such a way as to be enabled when the access circuit is enabled, and arranged in such a way as to exhibit a lower saturation current than the saturation current of the access circuit
Implementation Method 2
fusible elements, such as capacitors, that are 'blown' electrically, that is to say the dielectric of the capacitor is electrically impaired in an irreversible manner, so that the latter then behaves as a resistance of small value
Implementation Method 3
As regards the cells selected during programming, their reliability is affected by the phenomenon of hot carrier degradation. This reliability problem arises in particular for CMOS technologies at 65 nanometers and less, by virtue in particular of the strong current passing through the access transistor exhibiting a strong drain/source voltage
Data Source
AI summary
A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device.