Vertical Resistance Memory Read Method Block Segmentation

The memory array is divided into multiple blocks, and only a selected block is activated for read operations. String selection transistors are used to isolate specific strings within the selected block, while other blocks remain inactive. This segmentation prevents current leakage and measurement interference from unselected blocks, enabling accurate memory state determination of the selected cells.

String selection transistors act as intermediaries between the bit lines and the resistance memory cells. These transistors are selectively activated to enable current flow only through the desired string, blocking current leakage paths through unselected cells. This intermediary mechanism ensures that the read current accurately reflects only the state of the selected memory cell.

The three-dimensional memory array is segmented into multiple blocks along the vertical axis, with each block containing multiple strings. This hierarchical segmentation allows selective activation of specific blocks and strings, managing the complexity of reading from dense 3D structures by isolating only the necessary cells for each read operation.

The patent utilizes vertical stacking of multiple blocks to achieve three-dimensional storage density. By adding the vertical dimension with multiple blocks stacked above each other, the system increases storage capacity while maintaining manageable read operations through selective block activation. The vertical electrode connects cells across multiple blocks, enabling efficient access patterns.