AMPI Flash Memory Controller Parallel Read Sequencing
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Solution Overview
Problem
Current flash memory technologies face challenges in achieving high data rates and maintaining data bus integrity during parallel read operations across multiple memory planes without causing prolonged bus operations or missequenced read results.
Innovation Solution
The implementation of an asynchronous multi-plane independent (AMPI) read operation system, where a controller with shift registers and a signal generation circuit manages commands across multiple memory planes, allowing parallel processing while maintaining the original command sequence through an indicator signal, ensuring that commands are processed in the order received from the host.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel read operations are performed across multiple memory planes, then data access speed is improved, but data bus integrity and command sequencing may be compromised
Solution Approach 1:
The system segments memory operations by implementing independent read pipelines for different memory planes (e.g., plane 0, plane 1, plane 2, plane 3). Each plane can execute read commands simultaneously through dedicated shift registers and data output circuits, enabling parallel access while maintaining separate command sequences for each plane to ensure data integrity
Solution Approach 2:
The patent introduces an intermediary command sequencing mechanism that uses indicator signals and shift registers to mediate between parallel plane operations and the sequential data bus. This intermediary layer tracks command sequences for each plane independently and ensures that data is presented to the host in the correct sequential order, preventing bus conflicts and maintaining integrity
2Productivity
If multiple commands are processed simultaneously across memory planes, then productivity is improved, but command sequencing accuracy may deteriorate
Solution Approach 1:
The system performs preliminary actions by pre-configuring shift registers for each memory plane before executing parallel read operations. The shift registers are initialized to track command sequences, and indicator signals are prepared in advance to mark the status of each plane's command completion. This preliminary setup enables accurate sequencing without compromising processing speed
Solution Approach 2:
The patent implements feedback mechanisms through indicator signals that continuously monitor the status of each memory plane's command processing. When a read operation completes on a specific plane, the corresponding indicator signal is updated, providing feedback to the control logic. This feedback ensures that commands are completed and data is output in the correct sequential order, maintaining accuracy while enabling parallel processing
Data Source
AI summary
A flash memory device includes a plurality of memory planes each contains arrays of memory cells; a host interface for accessing the plurality of memory planes by an external host; and a controller connected to the plurality of memory planes via a memory interface and controlling the host interface for accessing the plurality of memory planes. The controller is configured to perform: receiving one or more commands on the host interface from the external host; determining whether to perform asynchronous multi-plane independent (AMPI) read operation corresponding to the commands; and after determining to start the AMPI read operation, accessing the memory planes in parallel according to the commands, and completing the AMPI read operation using an order of the commands determined based on an indicator signal provided to the controller to correspond to a sequence of the commands received on the host interface.