Flash Memory Programming with Dual Verify Voltage
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Solution Overview
Problem
Conventional programming methods for multi-bit flash memory devices result in wider threshold voltage distribution profiles due to F-poly coupling effects, leading to reliability issues during reading operations, especially as the number of data bits stored in a single memory cell increases.
Innovation Solution
A method involving a first and second verify-reading operation using different verifying voltages to program and reprogram memory cells, ensuring that under-programmed cells are identified and reconditioned to achieve a denser threshold voltage distribution profile, with the second verifying voltage being higher than the first to correct deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a smaller incremental rate of program voltage is used in ISPP scheme, then threshold voltage distribution is better controlled with sufficient margin between states, but programming time is lengthened
Solution Approach 1:
The patent divides the programming operation into two distinct phases: a first programming operation that programs memory cells in units of two adjacent word lines, and a second programming operation that reprograms selected memory cells individually based on verify reading results. This segmentation allows the system to achieve precise threshold voltage control without excessive programming time by processing most cells efficiently in batches and only revisiting cells that need correction.
Solution Approach 2:
The patent performs a preliminary programming operation on all selected memory cells before conducting verify reading operations. This preliminary action programs the majority of cells to their target states efficiently, and subsequent verify reading identifies only the minority of cells that require reprogramming due to coupling effects, thereby reducing overall programming time while maintaining precision.
2Quantity of substance
If multi-bit data is stored in a single memory cell to increase storage capacity, then storage density is improved, but threshold voltage distribution becomes wider due to F-poly coupling effects
Solution Approach 1:
The patent implements a feedback mechanism where verify reading operations are performed after the first programming operation to detect memory cells whose threshold voltages deviate from target values due to F-poly coupling effects. The system then uses this feedback information to selectively reprogram only those cells that failed verification, thereby correcting the threshold voltage distribution width while maintaining multi-bit storage capacity.
Solution Approach 2:
The patent changes the verification parameter by using different verifying voltages for different data states. By adjusting the verifying voltage levels according to the target threshold voltage ranges for each multi-bit data state, the system can accurately detect under-programmed cells and reprogram them to achieve the desired narrow threshold voltage distribution width.
3Productivity
If F-poly coupling effects are present during programming of adjacent memory cells, then programming speed is maintained, but threshold voltage distribution profile becomes wider reducing reliability
Solution Approach 1:
The patent extracts and isolates the problematic memory cells affected by F-poly coupling effects from the general programming process. By performing verify reading operations after initial programming and identifying only those cells that failed verification, the system separates the cells needing correction from those successfully programmed, allowing targeted reprogramming without affecting overall programming speed or introducing additional coupling effects.
Data Source
AI summary
A method is for programming a flash memory device which includes a plurality of memory cells storing multi-bit data representing one of a plurality of states. The method includes programming the multi-bit data into selected memory cells of the plurality of memory cells, the programming including a first verify-reading operation performed by a first verifying voltage, determining whether to execute a reprogramming operation for each of the selected memory cells, and reprogramming the selected memory cells in accordance with the determination. The reprogramming of the selected memory cells includes a second verify-reading operation performed by a second verifying voltage, the second verifying voltage being higher than the first verifying voltage.