P-channel Non-volatile Memory Erase via Substrate Hole Injection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing non-volatile memory technologies, such as SONOS devices, face issues with current leakage due to defects in the tunneling oxide layer, leading to decreased reliability and efficiency in erasing operations, particularly with the Fowler-Nordheim tunneling mechanism, which results in threshold voltage saturation and poor charge retention.
Innovation Solution
A method involving substrate hole injection is employed, where a low operational voltage is applied to inject holes into the charge storage structure, reducing power consumption and enhancing erasing efficiency by forming a depletion region and generating electron-hole pairs, allowing for efficient erasure without relying on the thickness of the bottom oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the Fowler-Nordheim tunneling mechanism is used to erase data in the SONOS memory cell, then the erasing operation can be performed, but the threshold voltage decreases with erasing time and gradually saturates, resulting in degraded erase performance
Solution Approach 1:
The patent changes the fundamental parameter of the erasing mechanism from Fowler-Nordheim tunneling (electron injection) to substrate hole injection. By applying a voltage difference between the substrate and drain region, holes are injected into the charge storage layer from the substrate, providing an alternative erasing mechanism that avoids the threshold voltage saturation problem
Solution Approach 2:
The patent introduces holes as an intermediary charge carrier to achieve erasure. Instead of directly removing electrons through tunneling, holes are injected as mediators that recombine with trapped electrons in the charge storage layer, effectively neutralizing the stored charge and erasing the data
2Productivity
If a higher voltage is applied to the control gate to improve erasing speed, then the erasing time can be reduced, but the power consumption increases
Solution Approach 1:
The patent changes the voltage application strategy from applying high voltage to the control gate to applying a moderate voltage difference between the substrate and drain region. This parameter change enables efficient hole injection without requiring excessively high control gate voltages, thus reducing power consumption while maintaining erasing speed
3Productivity
If the bottom oxide layer is made thinner to enhance electron tunneling efficiency, then the erasing efficiency improves, but the charge retention performance deteriorates
Solution Approach 1:
The patent uses holes as an intermediary mechanism that bypasses the need for thin bottom oxide layer. Since holes are injected from the substrate through the bulk material rather than tunneling through the oxide barrier, the bottom oxide thickness does not critically affect the erasing efficiency, allowing thicker oxide layers that provide better charge retention
Solution Approach 2:
The patent changes the erasing mechanism from electron tunneling (sensitive to oxide thickness) to hole injection (insensitive to oxide thickness). This parameter change decouples the relationship between oxide thickness and erasing efficiency, enabling the use of thicker oxide layers for improved charge retention without sacrificing erasing performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, accelerates erasing speed, and improves reliability by lowering the electric field stress on the charge storage structure, enabling faster and more stable erasure with improved charge retention and flexibility in device design.
Implementation Method 1
a voltage difference between the first voltage and the second voltage is sufficient to form a depletion region near the source/drain junction and under the control gate. Moreover, when the voltage difference between the first voltage and the second voltage is large enough to result in the impact ionization in the depletion region (near the source/drain junction), the electron-hole pairs will be generated
Implementation Method 2
when the voltage difference between the first voltage and the second voltage is large enough to result in the impact ionization in the depletion region (near the source/drain junction), the electron-hole pairs will be generated
Implementation Method 3
a voltage of −6 volts is applied to the control gate 114 to erase the data stored in the memory cell by the Fowler-Nordheim (F-N) tunneling mechanism
Data Source
AI summary
A present invention relates to a method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge storage structure by substrate hole injection effect. Hence, the applied operational voltage is low, so the power consumption is lowered, and the efficiency of erasing is enhanced. As a result, an operational speed of the memory is accelerated, and the reliability of the memory is improved.