Vertical Fuse Array Architecture for Memory Manufacturing
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Solution Overview
Problem
The complexity of manufacturing memory systems with vertical thin-film transistors (TFTs) and one-time programmable (OTP) arrays increases due to the need for different manufacturing operations, leading to higher manufacturing steps and machinery requirements.
Innovation Solution
The use of antifuses with semiconductor channels extending vertically from a substrate, coupled with oxide material and word/digit lines, allows for manufacturing techniques similar to those used for vertical TFTs, reducing complexity by leveraging shared manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vertical TFTs and OTP arrays are manufactured using different manufacturing operations, then the functionality of both components is achieved, but the manufacturing complexity and number of steps increase
Solution Approach 1:
The patent merges the manufacturing processes for vertical TFTs and OTP arrays by integrating the formation of semiconductor channels, oxide layers, and electrode structures into a unified process sequence. The same deposition and etching steps that create vertical TFT structures are simultaneously used to form OTP array structures, eliminating the need for separate manufacturing operations for each component type.
Solution Approach 2:
The manufacturing process is designed to be universal, where a single set of manufacturing operations can produce both vertical TFTs and OTP arrays. The process uses the same semiconductor material deposition, oxide layer formation, and electrode patterning steps to create different device structures based on the same fundamental process sequence, making the manufacturing system multi-functional.
2Productivity
If separate manufacturing processes are used for vertical TFTs and OTP arrays, then component-specific performance is optimized, but the number of manufacturing steps and machinery requirements increase
Solution Approach 1:
The patent combines multiple manufacturing operations into a single integrated process flow. The formation of semiconductor channels, oxide barriers, and electrodes is performed using the same deposition and patterning equipment for both vertical TFTs and OTP arrays, reducing the total number of manufacturing steps and minimizing the variety of specialized machinery required.
Solution Approach 2:
While merging processes, the patent maintains segmentation in the structural design where vertical TFTs and OTP arrays are formed as distinct device types within the same process framework. This allows component-specific performance optimization through structural variations while utilizing shared manufacturing operations, achieving both productivity and performance goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing of memory systems by reducing the number of manufacturing steps and machinery needed, while maintaining the functionality of vertical TFTs and OTP arrays.
Implementation Method 1
the dielectric material is configured to break down based at least in part on activating the switching component and applying the voltage to the second access line
Data Source
AI summary
Methods, systems, and devices for vertical fuse array architecture are described. A memory system may include a one-time programmable array of antifuses which are manufactured using techniques similar to manufacturing other components, layers, or both of the memory system. Each antifuse of the array may include a semiconductor channel extending vertically from a substrate and coupled with an oxide material. Each antifuse may further be coupled with a word line and a digit line, which may be configured to break down the oxide material to couple the digit line and word line. In some examples, the oxide material may be arranged on one or more sidewalls of the channel. Additionally or alternatively, the oxide material may be arranged on an upper surface of an upper terminal of the channel.