Nonvolatile Memory Write Voltage Adjustment for Layer Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In BiCS memory devices, the varying write characteristics across different layers and the increased stress from repeated write pulses lead to write failures, resulting in the formation of bad blocks and reduced device lifespan.
Innovation Solution
A nonvolatile semiconductor memory device that adjusts the write voltage based on the number of write operations stored for a sample string, ensuring uniform write characteristics across layers by using a register to hold and apply the necessary voltage adjustments for other memory cells in the same layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write pulses are applied repeatedly to memory cells in BiCS memory, then data can be written to memory cells, but write failures occur and bad blocks are formed due to varying write characteristics across layers and accumulated stress
Solution Approach 1:
The patent applies different write voltages to memory cells in different layers based on their specific write characteristics. The controller measures write characteristics for each layer and adjusts the write voltage locally for each layer, rather than using a uniform write voltage for all layers. This local optimization resolves the contradiction by enabling successful writes in each layer while preventing write failures and bad block formation.
Solution Approach 2:
The patent dynamically changes the write voltage parameter based on measured write characteristics. The controller measures the number of write pulses required for program verification and uses this information to adjust the write voltage for subsequent operations. This parameter adjustment optimizes write speed while preventing excessive stress accumulation that leads to write failures.
2Productivity
If the number of write operations is increased to ensure data is written, then write speed improves, but stress on memory cells increases leading to write failures
Solution Approach 1:
The patent implements a feedback mechanism where the controller measures write characteristics (number of write pulses required for program verification) and uses this feedback to optimize subsequent write operations. By monitoring write performance and adjusting write voltages based on this feedback, the system achieves efficient writes without applying excessive stress that would cause write failures.
Solution Approach 2:
The patent performs preliminary measurement of write characteristics before conducting full write operations. The controller measures the number of write pulses required for program verification in advance and uses this information to determine optimal write voltages for subsequent operations, preventing excessive stress accumulation before it occurs.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, write circuit, memory unit, and voltage generation unit. A plurality of strings is arranged in the memory cell array, each of which includes a plurality of memory cells connected to word lines. The write circuit selects a first string selected as a sample from the memory cell array, and writes data to the memory cell. The memory unit holds, for each word line, the number of write operations to each memory cell of the first string. When data is written to each memory cell of a second string other than the first string, the voltage generation unit generates an initial write voltage based on the number of write operations, which corresponds to the selected word line and is read out from the memory unit.