Segmented Memory Architecture for 3D NAND Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in increasing memory density in stacked memory arrays, such as three-dimensional NAND flash memory, is compounded by operational complexities that are not encountered in single-level memory arrays, including issues with capacitance and hot electron injection during access operations.
Innovation Solution
The implementation of memory segmentation, where memory cells are arranged in blocks with independent word lines and select lines, allowing for reduced capacitance and mitigating hot electron injection by isolating unselected memory segments during access, facilitates efficient operation and data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in stacked memory arrays to increase memory density, then memory capacity is improved, but operational complexity and capacitance increase
Solution Approach 1:
The memory array is divided into multiple independently operable blocks, each with its own word lines and select lines. This segmentation allows selective access to specific blocks, reducing the capacitive load on control lines and simplifying operational complexity while maintaining high memory density through the stacked three-dimensional architecture
2Quantity of substance
If memory cells are arranged in stacked memory arrays to increase memory density, then memory capacity is improved, but word line capacitance increases
Solution Approach 1:
The memory array is divided into multiple independently operable blocks, each with its own word lines and select lines. This segmentation allows selective access to specific blocks, reducing the capacitive load on control lines and simplifying operational complexity while maintaining high memory density through the stacked three-dimensional architecture
Solution Approach 2:
Different blocks of the memory array can be independently activated based on access requirements. By enabling only the necessary blocks and keeping others in a low-power state, the patent reduces overall capacitance and energy consumption while maintaining the high density capability of the stacked structure
3Quantity of substance
If memory cells are arranged in stacked memory arrays to increase memory density, then memory capacity is improved, but hot electron injection issues worsen
Solution Approach 1:
The memory array is divided into multiple independently operable blocks, each with its own word lines and select lines. This segmentation allows selective access to specific blocks, reducing the capacitive load on control lines and simplifying operational complexity while maintaining high memory density through the stacked three-dimensional architecture
Solution Approach 2:
The patent applies preliminary protective actions by carefully controlling voltage levels and timing sequences during programming operations. By pre-charging bit lines to appropriate voltages and using controlled pulse sequences, the patent prevents excessive hot electron injection that would occur with naive voltage application, thereby protecting against data retention issues while maintaining high density operation
Data Source
AI summary
Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.