Gradient Seeding Voltage Scheme for Memory Subsystem Program Disturb
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During programming operations in memory sub-systems, unselected memory cells experience 'program disturb' effects due to shared word lines, leading to charge retention issues and incorrect data retrieval.
Innovation Solution
An enhanced gradient seeding scheme is implemented, where a seeding voltage is applied with a controlled potential gradient across word lines, allowing residue electrons to flow and reducing electron barriers, thereby minimizing program disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a seeding voltage is applied during a program operation, then charge retention is improved, but residue electrons accumulate in the channel causing program disturb
Solution Approach 1:
The patent segments the word lines into different groups (first plurality, second plurality, third plurality) and applies different voltage levels to each group during the seeding phase. This segmentation allows the system to create a controlled potential gradient that facilitates electron removal from the channel while maintaining charge retention in selected cells, thereby resolving the contradiction between improving charge retention and preventing program disturb.
Solution Approach 2:
The patent applies local quality by creating different electrical conditions in different regions of the memory array. Specifically, it applies higher voltages to certain word lines (first plurality) compared to others (second plurality) during the seeding phase, creating localized electron barriers that prevent harmful electron migration while allowing necessary charge retention in specific regions.
2Quantity of substance
If multiple word lines share a common channel, then device density is improved, but electron barriers between cells are reduced leading to program disturb
Solution Approach 1:
The patent changes the voltage parameter applied to different word lines during the seeding phase to create electron barriers. By applying higher voltages to the first plurality of word lines compared to the second plurality, the system creates potential barriers that prevent electron migration between adjacent memory cells sharing the same channel, thereby maintaining data retrieval accuracy while preserving high device density.
3Object-generated harmful factors
If a high voltage is applied to purge residue electrons, then program disturb is reduced, but charge retention in selected cells is compromised
Solution Approach 1:
The patent segments word lines into multiple groups with different voltage levels during the seeding phase. The first plurality of word lines receives higher voltages to facilitate electron removal and reduce program disturb, while the second plurality receives lower voltages to maintain charge retention in selected cells. This segmented approach allows simultaneous achievement of both goals without compromising either.
Solution Approach 2:
The patent uses the seeding phase as an intermediary step between erase and program operations. During this intermediate phase, controlled voltages are applied to word lines to gradually remove residue electrons from the channel without directly affecting the charge retention in selected memory cells, thereby mediating between the conflicting requirements of reducing program disturb and maintaining charge retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced gradient seeding scheme effectively purges residue electrons from the memory cell channel, reducing program disturb and improving data retention and retrieval accuracy during subsequent program operations.
Implementation Method 1
a seeding voltage is applied with a controlled potential gradient across word lines, allowing residue electrons to flow
Data Source
AI summary
Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.