Flash Memory Over-Erase Correction via Bit Line Leakage Current Selection
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Solution Overview
Problem
The existing over erase correction methods for flash memory arrays are inefficient and power-intensive, leading to ineffective correction due to excessive bit line leakage current, which can cause read errors and programming failures, especially when the charge pump voltage drops below a certain threshold.
Innovation Solution
The method involves controlling a column decoder to selectively output control signals to a bit line exchange unit based on the magnitude of bit line leakage current, allowing for efficient over erase correction by alternating the selection of bit lines during the correction process, thereby reducing power consumption and maintaining effective voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bit lines are selected during over erase correction, then correction effectiveness is improved, but power consumption increases due to huge leakage current
Solution Approach 1:
The patent divides the bit lines into multiple groups and selects only a subset of bit lines for over erase correction at any given time, rather than correcting all bit lines simultaneously. This segmentation approach reduces the total leakage current drawn from the charge pump while still achieving correction effectiveness across the entire memory array through multiple correction cycles.
2Productivity
If all gates are biased positively to reduce correction time, then productivity is improved, but charge pump voltage drops below threshold making correction ineffective
Solution Approach 1:
The patent applies different voltage biases to different groups of word lines during over erase correction. Specifically, some word lines are biased at 0V while others are biased at a positive voltage, allowing selective correction of specific bit line groups. This local differentiation enables the charge pump to maintain sufficient voltage levels for effective correction while reducing total power consumption.
3Use of energy by moving object
If bit line leakage current is reduced by selective selection, then power consumption is reduced, but correction time increases
Solution Approach 1:
The patent implements over erase correction in multiple periodic cycles, where each cycle corrects a subset of bit lines. Between cycles, the system can reconfigure the bit line selections and apply fresh charge pump voltage. This periodic approach distributes the correction task over time, maintaining lower power consumption per cycle while achieving complete correction across all bit lines through repeated cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces bit line leakage and ensures successful over erase correction while minimizing power usage, even when the charge pump voltage is low, thus preventing read errors and programming failures.
Implementation Method 1
drains of the cells are biased with a charge pump voltage, which is couple to the corresponding bit lines, and thus, the hot electrons are injected into the floating gate again to increase the threshold voltage of the cells
Implementation Method 2
the hot electrons are injected into the floating gate again to increase the threshold voltage of the cells
Implementation Method 3
Fowler-Nordheim (FN) tunneling is typically applied to a cell of the flash memory, which pulls electrons from a floating gate of the cell through a tunneling oxide layer to a channel region in the cell
Data Source
AI summary
An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the column decoder outputs control signals to the bit line exchange unit for selecting at least one of the bit lines according to a magnitude of the bit line leakage current. The drop in the charge pump voltage due to the bit line leakage current is reduced, and thus, the over-erase correction is executed effectively during the period of the over-erase correction.