Adaptive Flash Memory Erase Bias Voltage Control
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Solution Overview
Problem
Conventional flash memory devices use fixed erase bias voltages, which can lead to unnecessary degradation in newer devices and prolonged erase times for highly cycled cells, as they are selected for the 'worst case scenario' and do not adapt to the current erase characteristics of the device.
Innovation Solution
An adaptive erase bias voltage scheme is employed, where erase pulses are counted during a preliminary operation, and the bias voltages are dynamically adjusted based on the count to optimize erase operations for the specific sector, allowing for sector-by-sector adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed erase bias voltages are used for all memory cells, then erase operation can be completed for highly cycled cells, but device degradation occurs in newer devices and erase times are prolonged
Solution Approach 1:
The patent implements dynamic adjustment of erase bias voltages based on the cycling history and characteristics of each memory sector. Instead of using fixed voltages for all cells, the system adapts the voltage levels dynamically - applying lower voltages to newer sectors and higher voltages to highly cycled sectors, thereby eliminating unnecessary degradation while maintaining effective erasure capability
Solution Approach 2:
The patent applies different erase bias voltages to different sectors based on their individual erase characteristics and cycling history. Each sector receives a tailored voltage level suited to its specific condition, rather than applying a uniform voltage across the entire memory device, thus optimizing the balance between erasure effectiveness and device protection
2Reliability
If fixed erase bias voltages selected for worst case scenario are used, then all memory cells can be erased reliably, but erase times are prolonged for non-highly cycled cells
Solution Approach 1:
The system dynamically determines the appropriate erase bias voltage for each sector based on its cycling history and erase characteristics. By adapting the voltage level to the specific needs of each sector, the system achieves complete erasure reliability while minimizing erase time - applying only the necessary voltage duration to each sector rather than using a conservative fixed voltage for all cells
Solution Approach 2:
The patent changes the erase bias voltage parameter based on the sector's cycling history and erase characteristics. By adjusting this critical parameter dynamically, the system optimizes the erasure process to achieve complete data removal in the minimum necessary time for each specific sector condition
Data Source
AI summary
A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase pulse count corresponding to a preliminary erase operation during which a relatively small portion of a sector is erased. The adjustment of the erase bias voltage in this manner enables the rest of the sector to be erased using erase bias voltages that are better suited to the current erase characteristics of the sector.