Read-Only Memories TRIZ Cases
- Blank State Detection in Differential Read Memory Using Time Domain Conversion
Converting current to time domain signals allows blank state detection without additional analog circuitry, maintaining high read performance.
- Non-Volatile Memory Programming With Dynamic Bitline Bias
Segmented bitline bias voltages narrow threshold voltage distributions and reduce read noise errors while maintaining fast programming speed.
- Nonvolatile Memory Programming Voltage Adaptation
A nonvolatile memory programming method adjusts the program start voltage based on erase pulse counts to optimize cell performance.
- NAND Read Voltage Adjustment for Read Disturb Mitigation
Adjusting read voltages via a counter mitigates data integrity loss from read disturb effects in 3D NAND memory arrays.
- Analog Solid State Memory Bit Pattern Programming
Memory devices utilize analog signals to represent complete bit patterns, reducing operation times and increasing storage capacity per cell.
- Sequential Memory Access Method Eliminates Discharge Periods
A sequential memory method equalizes transistor terminals to ground voltage during pre-discharge periods.
- Flash Memory Bad Block Remapping Using Existing Address Signals
A non-volatile memory device remaps bad blocks using existing block address signals to select redundant cells.
- Simplified Page Buffer Structure for Memory Devices
Integrating data storage and voltage stabilization into the latch circuit reduces space occupation while maintaining signal transmission accuracy.
- Flash Memory Metablock Size Reduction via Plane Interleaving
Segmenting metablocks into sub-units enables parallel plane writes while maintaining standard compliance, reducing programming time.
- Flash Memory Sense Architecture Flexible Sector Routing
Differential sense amplifier architecture pairs adjacent column groups to reduce chip area and parasitic impedances in flash memory arrays.
- Flash Memory Selective Bitline Precharging for Power Reduction
Selective bitline precharging reduces power consumption by isolating error correction operations to target sectors, extending flash memory device lifespan.
- Memory Device Password Storage Segmentation
Segmenting passwords into partial bit strings across spaced-apart memory areas prevents fraudulent acquisition of the complete credential.
- Fuseless Fuse Structure for Re-programmable IC Configuration
A fuseless fuse structure uses a wrapper and JTAG registers to store configuration data in integrated circuits.
- Fuse Cell Adjustable Sensing Margin Asymmetry
Resolves low resistance sensing issues by configuring asymmetric voltage adjustments across fuse cell branches.
- Pre-conditioning Waveforms for Non-Volatile Storage Read Accuracy
Pre-conditioning waveforms stabilize non-volatile storage elements before read operations to enhance data decoding accuracy.
- NAND Memory Reference Voltage Offset Lookup Table
A lookup table maps 1-bit count difference voltage offsets to optimal reference voltage adjustments for NAND memory storage systems.
- Semiconductor Integrated Circuit Level Shift Transistor Signal Amplitude Control
A semiconductor integrated circuit uses a level shift transistor to reduce signal amplitude on transmission lines.
- SRAM Sense Margin Improvement via Lower Threshold Voltage Transistors
Lower threshold voltage transistors in column multiplexers increase bit line voltage levels for improved sense margins.
- Page Buffer Switching Device Area Reduction via Series Voltage Elements
Series high and low voltage elements in a page buffer switch reduce memory device area while maintaining erase functionality.
- Flash Memory Dual Supply Operation via Internal Voltage Generation
An internal voltage generator converts external high voltage to low voltage, enabling dual supply operation without additional pins.
- Nonvolatile Memory FN Tunneling Electric Field Concentration
A nonvolatile memory structure uses electric field concentration to enable efficient Fowler-Nordheim tunneling for electron injection.
- Memory Controller Thermal Throttling via Dynamic Status Read Check Period
A memory controller adjusts the status read check period for target dies based on threshold voltage distribution offset.
- Quarter Match Concurrent Compensation in Memory Row Redundancy
Quarter match signals halt prime row sensing early to trigger concurrent threshold voltage compensation, reducing tRCD delay.
- Split Address ROM for High-Speed Fault Detection in Memory Arrays
Segmenting the address ROM allows parallel processing of wordline addresses, resolving speed versus complexity trade-offs in split array memory systems.
- Electrical Fuse Rupture Circuit for Semiconductor Memory Repair
An internal feedback loop in the fuse rupture circuit verifies operations automatically, reducing testing time and improving manufacturing yield.
- Dynamic Read Voltage Adjustment for Memory Cell Data Retrieval
Controller calculates average threshold voltages to set a temporary read voltage for memory cells.
- Adaptive Flash Memory Erase Bias Voltage Control
Dynamic erase bias voltage adjustment optimizes flash memory sector erasure, reducing device degradation and shortening erase times for highly cycled cells.
- Semiconductor Memory Redundancy Arrays for Defect Repair
Variable redundancy arrays repair defects across memory areas, increasing manufacturing yield.
- Fuse Circuit Sequential Latch Reset for Peak Current Reduction
A fuse circuit segments latch groups and sequentially enables reset signals to stabilize data storage.
- Flash Memory Voltage Adjustment for Read Reliability
Dynamically varies non-selected word line voltages by position to minimize source resistance and ensure timely bit-line discharge during read operations.
- Nonvolatile Memory Core Bias Line Stabilization Circuit
A stabilization circuit regulates the core bias line voltage in nonvolatile memory devices using active compensation.
- Nonvolatile Memory Word Line Programming Interference Reduction
A nonvolatile memory operation method adjusts verify voltages based on calculated delay times between sequential word line programming stages.
- OTP Memory Cell Switching Circuit for Multi-Bit Programming
Switching circuit detects program states to block currents, reducing voltage drop and program time in OTP memory devices.
- Semiconductor Memory Device Flag Cell Read Voltage Control
A semiconductor memory device uses distinct read voltages for flag cells and data cells to determine stored states accurately.
- NAND Memory Channel Gradient for Read Disturb and Power Reduction
Creating a channel potential gradient in floated NAND strings prevents read disturb while reducing power consumption.
- Nonvolatile Memory Multi-Read Command Architecture
A nonvolatile memory device executes a multi-read command to access multiple target pages via sequential voltage application.
- Memory Controller Segmentation for Mixed Volatile Non-Volatile DDR Access
Segmenting volatile and non-volatile memory allows the controller to mask slower access times, enabling mixed latency DIMMs on one interface.
- Flash Memory Column Decoder Transistor Segmentation
Segmenting bit line control between low and high voltage transistors reduces the column decoder footprint in flash memory arrays.
- Voltage Generation Circuit for Sense Amplifier Stabilization
Segmented current circuits generate intermediate and final voltages to reduce stabilization time for semiconductor storage devices.
- NAND Flash Memory Bit Line Precharge via Segmentation and Equipotentiality
Segmenting bit line precharge phases and maintaining equipotential conditions between adjacent lines reduces RC time constants from 10 μs to 1-2 μs.
- Bias Voltage Schemes for Dummy Wordlines in Memory Programming
Dynamic bias voltage schemes adjust dummy wordline potentials to minimize potential gradients and prevent hot carrier injection.
- Memory Peripheral Circuit Parallel Initialization
Peripheral circuit overlaps initialization with program data reception, reducing program time while maintaining memory reliability.
- Flash Memory Cell Array Segmentation for Leakage Current Control
Segmented memory block units with independent common source lines and switching units manage voltage application in flash memory arrays.
- Antifuse Replacement Determination Circuit for Semiconductor Memory
A semiconductor antifuse replacement determination circuit charges a node to a predetermined voltage and allows self-discharge before comparing the voltage with multiple reference levels.
- 3D NAND Initialization via Dummy String Selection Line
Programming string selection transistors with a dummy line achieves sharp threshold distributions without interlayer disturbances in 3D NAND devices.
- Multilevel Memory Cell Grouping for Silicon Area Reduction
Encoding bit groups into multilevel cell pairs reduces silicon area occupation by minimizing the number of cells required per page.
- Asymmetric Boosting Read with Look-Back for Memory Disturb
Read with look-back selects voltages based on adjacent cell states to resolve program disturb and improve data retention accuracy.
- Memory Controller Bit Line Voltage Control for Write Disturb Prevention
A memory controller supplies specific unselected bit line voltages to maintain logic states in inhibited cells during write operations.
- Oxide Semiconductor Transistor Driving Method for Data Retention
Inverted period driving method suppresses transient current in oxide semiconductor transistors.