Nonvolatile Memory Word Line Programming Interference Reduction
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Solution Overview
Problem
Flash memory devices experience degradation due to coupling between word lines, leading to reduced reliability, as the program voltage causes interference affecting adjacent memory cells.
Innovation Solution
An operation method for a nonvolatile memory device that involves a 1-stage and 2-stage program operation, where a program voltage and verify voltages are adjusted based on delay times and cell count differences to minimize interference between word lines, ensuring accurate programming and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program voltage is applied to a selected word line to program memory cells, then the programming operation is completed, but degradation occurs in memory cells of adjacent word lines due to coupling interference
Solution Approach 1:
The patent divides the programming operation into two distinct stages: a first programming stage that programs a first word line, and a second programming stage that programs a second word line adjacent to the first. This segmentation allows the system to complete programming of one word line before proceeding to the next, thereby preventing coupling interference from affecting adjacent memory cells during the programming process.
Solution Approach 2:
The patent performs preliminary actions by completing the first programming stage and verifying the programming of the first word line before initiating the second programming stage. This preliminary completion and verification ensure that adjacent memory cells are not subjected to interference from subsequent programming operations, as the programming sequence is carefully controlled to eliminate overlapping voltage applications.
2Productivity
If programming operations are performed on multiple word lines, then productivity increases, but interference between word lines increases leading to degradation
Solution Approach 1:
The patent segments the multi-word line programming operation into sequential stages, where each stage programs a specific word line completely before moving to the next. This segmentation maintains high productivity by systematically progressing through multiple word lines while ensuring that each programming operation is completed and verified before the next begins, thus preventing interference-related degradation.
Solution Approach 2:
The patent incorporates verification steps between programming stages, where the programming status of the first word line is verified before proceeding to program the second word line. This feedback mechanism ensures that programming operations are completed successfully without causing degradation in adjacent memory cells, maintaining both productivity and reliability by detecting and addressing any issues before they propagate.
Data Source
AI summary
An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.