Non-Volatile Memory Programming With Dynamic Bitline Bias
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Solution Overview
Problem
Current programming methods for non-volatile memory devices, such as flash memory, face challenges in achieving narrow threshold voltage distributions due to instant threshold voltage shift and read noise or random telegraph noise, which compromise reliability and programming speed.
Innovation Solution
The method employs incremental step pulse programming with multiple bitline bias voltages, including a low voltage, two intermediate voltages, and a system voltage, to dynamically adjust bitline bias based on threshold voltage comparisons across programming loops, ensuring efficient programming while addressing instant threshold voltage shifts and noise-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If incremental step pulse programming is used to achieve fast programming, then programming speed is improved, but threshold voltage distribution becomes wider due to instant threshold voltage shift
Solution Approach 1:
The patent segments the bitline bias voltage into multiple levels (first bitline bias voltage and second bitline bias voltage) to differentially treat cells based on their programming status. Easy cells receive one voltage level while hard cells receive another, allowing the system to maintain fast programming speed for easy cells while providing additional programming assistance to hard cells, thereby narrowing the threshold voltage distribution without sacrificing overall programming speed.
Solution Approach 2:
The patent changes the bitline bias voltage parameter dynamically during the programming process. By switching between different bitline bias voltage levels based on verify results, the system adapts the programming conditions to address instant threshold voltage shift. This parameter change allows cells that experience threshold voltage shift to receive enhanced programming voltage in subsequent iterations, narrowing the distribution while maintaining fast initial programming.
2Reliability
If multiple verify operations are performed to reduce noise-related errors, then reliability is improved, but programming speed decreases
Solution Approach 1:
The patent applies partial verify operations rather than full multiple verify sequences. By performing verify checks at strategic points and using bitline bias voltage adjustments to correct errors, the system achieves noise-related error reduction without implementing complete multiple verify operation sequences. This partial action approach maintains programming speed while improving reliability through targeted error correction.
Solution Approach 2:
The patent implements feedback mechanisms where verify results are used to determine subsequent bitline bias voltage levels. The verify operation provides feedback about cell status, and this feedback drives the selection of appropriate bitline bias voltages for the next programming iteration. This feedback loop enables the system to address noise-related errors efficiently without requiring multiple complete verify sequences, thus maintaining programming speed while improving reliability.
3Device complexity
If a single bitline bias voltage is used during programming, then device complexity is reduced, but the ability to handle instant threshold voltage shift and noise is compromised
Solution Approach 1:
The patent introduces dynamic bitline bias voltage control where the voltage level changes based on cell response during programming. Instead of a static single voltage level, the system dynamically switches between first and second bitline bias voltages based on verify results and cell characteristics. This dynamic approach enhances reliability by adapting to instant threshold voltage shift and noise conditions while adding only moderate complexity through conditional voltage selection logic.
Solution Approach 2:
The patent applies different bitline bias voltage levels to different cells or cell groups based on their individual programming characteristics. Easy cells receive one voltage level while hard cells receive another, creating local quality differences in the programming approach. This localized treatment improves reliability for each cell type without requiring complex global control mechanisms, as the system simply applies appropriate voltage levels based on verify results.
Data Source
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AI summary
Programming in a non-volatile memory device includes applying at least one programming pulse to a non-volatile memory cell during a first programming loop; applying at least one programming pulse to the non-volatile memory cell during a second programming loop succeeding the first programming loop; and providing a bitline bias voltage of the non-volatile memory cell according to a result of comparing a threshold voltage of the non-volatile memory cell in the first programming loop with a low verify level and/or a high verify level of a target data state of the non-volatile memory cell and a result of comparing a threshold voltage of the non-volatile memory cell in the second programming loop with the low verify level and/or the high verify level of the target data state of the non-volatile memory cell.