Split Address ROM for High-Speed Fault Detection in Memory Arrays
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Solution Overview
Problem
Current address fault detection methods in integrated circuit memories are inadequate for rapid detection of address faults and wordline continuity faults, particularly in split array memory systems, where faults can lead to errors in wordline selection and drive voltage failure due to continuity issues across the array.
Innovation Solution
The implementation of a split address ROM and associated detection logic, where two separate address ROMs handle different portions of the wordline address, allowing for rapid detection of address faults and wordline continuity faults across both sides of a split memory array, by generating fault indicator signals that combine outputs from each ROM to provide a comprehensive fault indication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single address ROM is used for fault detection, then the device complexity is reduced, but the fault detection speed and accuracy deteriorate
Solution Approach 1:
The patent divides the single address ROM into multiple separate address ROMs, each handling a specific portion of the wordline address. This segmentation allows parallel processing of different address portions, thereby increasing fault detection speed while maintaining manageable complexity through modular design
2Measurement precision
If address ROM covers the entire wordline address, then comprehensive fault detection is achieved, but the detection time increases
Solution Approach 1:
The patent segments the address ROM functionality across multiple parallel ROM units, each processing a portion of the address simultaneously. This enables comprehensive fault detection across the entire wordline address space while reducing detection time through parallel operation
Solution Approach 2:
Each address ROM processes only a specific portion of the wordline address rather than the complete address, allowing partial processing that occurs in parallel. The combination of these partial results achieves complete fault detection faster than a single ROM could process the entire address
Data Source
AI summary
High-speed address fault detection is described that uses a split address ROM (read only memory) for address fault detection in split array memory systems. In one aspect, a disclosed embodiment includes separate arrays of memory cells having a plurality of wordlines and being configured to be accessed based upon a wordline address. Two or more separate address ROMs are also provided with each address ROM being associated with a different one of the separate arrays and being configured to provide outputs based upon only a portion of the wordline address. Detection logic is coupled to the outputs from the address ROMs and is configured to provide one or more fault indicator outputs to indicate whether an address fault associated with the wordline address has occurred. The outputs form the address ROMs can also be used for wordline continuity fault detection. Other embodiments are also described.