NAND Flash Memory Bit Line Precharge via Segmentation and Equipotentiality
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Solution Overview
Problem
NAND flash memory devices face prolonged precharging times for bit lines due to large RC time constants, which hinder efficient data read operations.
Innovation Solution
Precharging adjacent data lines to the same voltage during a read operation, while maintaining the unselected line at that voltage, reduces parasitic capacitive coupling and facilitates faster precharge times by using dummy memory cells to isolate helper sources and control bit line voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If bit lines are precharged using conventional methods, then data read operations can be performed, but precharge time is excessively long (approximately 10 μs) due to large RC time constants
Solution Approach 1:
The bit line precharging process is segmented into two independent phases: first precharging the data line to a first voltage level, then precharging the same line to a second voltage level. This segmentation allows each phase to be optimized independently, reducing the total precharge time from 10 μs to 1-2 μs while maintaining read operation functionality.
Solution Approach 2:
The patent applies preliminary action by precharging the bit line to an intermediate voltage level before the final read operation. This preliminary precharge reduces the voltage swing required during the actual read, thereby reducing the RC time constant effect and enabling faster subsequent precharging to the final voltage level.
2Loss of time
If bit lines are precharged to reduce time, then precharge time decreases, but parasitic capacitive coupling increases which can interfere with signal integrity
Solution Approach 1:
The patent applies preliminary anti-action by precharging adjacent non-selected bit lines to the same voltage level as selected bit lines before the read operation begins. This preemptive action eliminates voltage differences between adjacent lines, thereby preventing parasitic capacitive coupling from causing signal interference during the fast precharge operation.
Solution Approach 2:
The patent creates equipotential conditions by maintaining all bit lines (both selected and non-selected) at the same voltage level during the precharge phase. This equipotential state eliminates electric field differences between adjacent lines, reducing parasitic capacitive coupling effects while enabling faster precharge times.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces precharge times from approximately 10 μs to 1-2 μs, enhancing the speed and efficiency of data read operations in NAND flash memory devices.
Implementation Method 1
This approach significantly reduces precharge times from approximately 10 μs to 1-2 μs, enhancing the speed and efficiency of data read operations in NAND flash memory devices
Data Source
AI summary
Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.