Semiconductor Memory Redundancy Arrays for Defect Repair
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Solution Overview
Problem
The increasing cost of semiconductor memory devices due to reduced chip size and manufacturing costs, which can be further exacerbated by bit errors that restrict yield improvement.
Innovation Solution
Incorporating a redundancy cell array in semiconductor memory devices to repair defective cells, with a larger redundancy cell array in a system memory area for bit-unit defects and smaller ones in data memory areas for row-unit/column-unit defects, and using an address indicating unit to facilitate address replacement between memory areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chip size is reduced to lower manufacturing costs, then device cost decreases, but manufacturing precision requirements increase and yield decreases due to bit errors
Solution Approach 1:
The memory device is divided into multiple memory areas (first memory area, second memory area, third memory area) with different redundancy configurations. System memory areas use larger redundancy arrays for bit-unit defect repair, while data memory areas use smaller redundancy arrays for row/column-unit defect repair, allowing differentiated reliability management across segments
Solution Approach 2:
The redundancy cell array size is varied across different memory areas based on their specific requirements. The first memory area (system memory) has a larger redundancy cell array to repair bit-unit defects, while the second and third memory areas (data memory) have smaller redundancy cell arrays for row/column-unit defects, optimizing the balance between cost and reliability
2Reliability
If redundancy cell arrays are added to repair defective cells, then device reliability increases, but device complexity and chip area increase
Solution Approach 1:
Different memory areas are assigned different redundancy cell array sizes according to their specific reliability requirements. The first memory area (system memory) receives a larger redundancy array for bit-unit defect repair, while data memory areas receive smaller redundancy arrays for row/column-unit defects, avoiding uniform over-provisioning
Solution Approach 2:
Instead of providing full redundancy coverage for all memory areas, the patent applies partial redundancy - smaller redundancy arrays in data memory areas that repair only row/column-unit defects, and larger redundancy arrays only in system memory areas where bit-unit defects must be repaired, reducing overall complexity
3Reliability
If address replacement between memory areas is implemented, then yield increases by utilizing defect-free areas, but device complexity increases due to address management
Solution Approach 1:
An address indication unit is introduced as an intermediary component that manages address mapping between physical memory areas and logical addresses. This unit automatically handles the complexity of address replacement when defective cells are detected, allowing defect-free memory areas to be utilized without burdening the control logic
Solution Approach 2:
The memory device performs self-diagnosis and self-reconfiguration through the address indication unit, which automatically detects defective cells and redirects addresses to functional memory areas without external intervention, enabling yield improvement through automated defect management
Data Source
AI summary
A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.