OTP Memory Cell Switching Circuit for Multi-Bit Programming

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Solution Overview

Problem

One-time programmable (OTP) memory devices require high voltage and long program times, leading to undesirable side effects and inefficiencies.

Innovation Solution

The OTP memory device incorporates a memory cell array with antifuses and transistors, utilizing a switching circuit to detect program states and block currents, allowing for multi-bit programming by applying specific voltages and controlling the switching transistors to manage current flow, thereby reducing voltage drop and program time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high voltage is applied for programming OTP memory cells, then the antifuse can be programmed, but voltage drop occurs and program time increases

Engineering Contradiction:
Improveprogramming capabilityVSAvoidprogram time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the memory cell array into multiple banks and further segments cells into groups that can be programmed independently. This segmentation allows parallel programming operations across different banks, reducing overall program time while maintaining the necessary high voltage for reliable antifuse programming.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary voltage to wordlines and bitlines before the actual programming operation begins. This preliminary action prepares the electrical conditions for programming, enabling faster and more efficient antifuse breakdown while reducing the total program time required.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If high voltage is applied for programming OTP memory cells, then the antifuse can be programmed, but side effects increase

Engineering Contradiction:
Improveprogramming capabilityVSAvoidside effects
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies high voltage only to the specific banks and cell groups that require programming, rather than applying voltage universally across the entire memory array. This localized approach ensures reliable programming of target cells while minimizing voltage-induced side effects on non-programmed cells and surrounding circuitry.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces switching circuits and control logic as intermediaries between the voltage source and the memory cells. These intermediaries precisely control when and where high voltage is applied, enabling reliable antifuse programming while isolating and minimizing harmful side effects through controlled voltage distribution.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If current flows through programmed antifuses during multi-bit program, then voltage drop increases, but blocking current requires additional switching circuits

Engineering Contradiction:
Improveprogram timeVSAvoidswitching circuit complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments the memory array into multiple banks with independent switching control. Each bank has its own switching circuits that can independently block or allow current flow. This segmentation enables efficient current management during multi-bit programming, reducing voltage drop without requiring a single complex switching circuit for the entire array.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The switching circuits in the patent serve multiple functions: they select which banks to program, control current flow during programming, block current after programming to prevent voltage drop, and enable parallel operation across banks. This multi-functionality reduces the need for additional dedicated circuits, balancing complexity with performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9524795B2One-time programmable (OTP) memory cell and OTP memory device for multi-bit program
Publication Date: 2016.12.20 SAMSUNG ELECTRONICS CO LTD
  • US9524795B2 patent drawing
  • US9524795B2 patent drawing
  • US9524795B2 patent drawing

AI summary

A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states.