Flash Memory Column Decoder Transistor Segmentation
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Solution Overview
Problem
The challenge in miniaturizing flash memory devices lies in reducing the size of the column decoder, which is hindered by the large size of high voltage transistors required for controlling bit lines, leading to difficulties in pitch pattern formation and increased risk of breakdown during erase operations, affecting the durability and capacity of the memory devices.
Innovation Solution
The configuration reduces the number of high voltage transistors by equipping each bit line string with only two, allowing for a more compact design and integration, while implementing a controlled voltage management system to prevent breakdowns during erase operations by clamping bit line voltages below the breakdown threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage transistors are used to control bit lines during erase operations, then the memory device can withstand high voltage stress, but the transistor size increases leading to larger column decoder area
Solution Approach 1:
The patent divides the bit line control function between two types of transistors: low voltage transistors for normal operation and high voltage transistors exclusively for erase operations. This segmentation allows each transistor type to be optimized for its specific function, with high voltage transistors being smaller than conventional designs since they only need to handle erase operations rather than all operations.
Solution Approach 2:
The patent applies preliminary voltage management by pre-charging bit lines to specific voltages before erase operations and using control logic to prepare the high voltage transistors in advance. This preliminary action ensures that high voltage stress is applied only when necessary and for minimal duration, reducing the required transistor size while maintaining reliability.
2Area of stationary object
If the column decoder area is reduced for miniaturization, then chip size decreases, but pitch pattern formation becomes difficult and short-circuiting risk increases
Solution Approach 1:
The patent segments the transistor gate length requirements by using different gate lengths for different functions: shorter gate lengths for low voltage transistors and slightly longer gate lengths for high voltage transistors. This segmentation allows the column decoder to be compact while maintaining manufacturable pitch patterns, as each transistor type can be optimized for its voltage requirements rather than using a uniform large size.
Solution Approach 2:
The patent changes the voltage parameter management by introducing controlled voltage phases (pre-charge, erase, recovery) and adjusting bit line voltages dynamically. This parameter change allows the use of smaller transistors with manageable pitch patterns, as the voltage stress is controlled and time-limited rather than continuous, reducing the required transistor dimensions while maintaining reliability.
3Productivity
If high voltage is applied to the well for erase operations, then data can be erased from memory cells, but voltage breakdown occurs in column decoder transistors
Solution Approach 1:
The patent implements preliminary voltage preparation by pre-charging bit lines to appropriate voltages before erase operations and activating high voltage transistors only when needed. This preliminary action ensures that voltage transitions are controlled and minimized, preventing breakdown while maintaining erase capability.
Solution Approach 2:
The patent uses rapid voltage switching to apply high voltage to the well only for the minimal duration necessary to perform the erase operation, then quickly returning to low voltage states. This 'rushing through' the high voltage state reduces cumulative stress on transistors while maintaining erase effectiveness, preventing breakdown through time-limited exposure.
4Device complexity
If the number of high voltage transistors is reduced for compact design, then integration increases, but voltage control during erase operations becomes challenging
Solution Approach 1:
The patent merges the voltage control function into a centralized control logic unit that manages all high voltage transistor operations. This control logic integrates pre-charge signals, erase enable signals, and recovery control into a unified system, simplifying the operation of reduced high voltage transistor counts while maintaining proper voltage management during erase operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables further miniaturization and higher integration of flash memory devices, reduces the failure ratio of short-circuiting, and enhances the durability by preventing high voltage stress during erase operations, thus supporting repeated usage and larger storage capacities.
Implementation Method 1
an erase voltage of approximately twenty volts is then usually applied to the entirety of a well 102 in which a memory cell array is placed. This causes any electrons accumulated in the floating gate of the selected memory cell to discharge to the well by virtue of a tunnel effect.
Data Source
AI summary
Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.