NAND Read Voltage Adjustment for Read Disturb Mitigation
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Solution Overview
Problem
Traditional 2D flash memory arrays face limitations in memory density and cost due to the size constraints of individual memory cells, prompting the development of 3D NAND architecture to increase capacity and reduce costs, but they struggle with read disturb effects that can alter data integrity, requiring time-consuming error correction and resource-intensive scanning.
Innovation Solution
Implementing a read counter mechanism that adjusts read voltages based on the number of read operations to compensate for read disturb effects, shifting voltages to maintain data integrity and extend the lifespan of memory cells before data is moved and erased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND architecture is used to increase memory density, then memory capacity and cost are improved, but read disturb effects worsen data integrity
Solution Approach 1:
The patent applies preliminary action by adjusting read voltages before actual read operations occur. A read counter tracks the number of read operations, and based on this count, the read voltage is proactively adjusted to compensate for read disturb effects before they can significantly alter data integrity. This preventive approach allows 3D NAND to maintain high capacity while mitigating read disturb issues.
2Reliability
If traditional error correction and scanning are used to maintain data integrity, then data accuracy is improved, but time consumption and resource usage increase
Solution Approach 1:
The patent converts the harmful read disturb effect into a beneficial mechanism by using the read counter and voltage adjustment to proactively manage data integrity. Instead of reactively applying time-consuming error correction after read disturb occurs, the system proactively adjusts read voltages based on read history, preventing data corruption before it happens. This eliminates the need for frequent error correction operations.
3Reliability
If read voltages are adjusted based on read counter, then data integrity is maintained, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the read voltage parameter based on the read counter value. Instead of adding complex hardware circuits, the solution modifies the electrical parameter (voltage level) according to the number of previous read operations. This simple parameter adjustment approach maintains data integrity while adding minimal complexity to the existing memory control architecture.
Data Source
AI summary
Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.