Simplified Page Buffer Structure for Memory Devices
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Solution Overview
Problem
As the integration level of memory increases, the area occupied by the page buffer in the peripheral circuit of memory devices decreases, requiring a reduction in the number of elements constituting the page buffer, which leads to increased space occupation and reduced energy efficiency in memory devices.
Innovation Solution
The page buffer structure is simplified to reduce space occupation and fabrication costs, comprising a bit line control circuit, a bit line discharge circuit, and a plurality of latch circuits, with a reduced number of transistors and a voltage stabilizing circuit to improve signal transmission accuracy and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of elements constituting the page buffer is reduced, then the space occupied by the page buffer decreases, but the manufacturing precision and reliability may be compromised
Solution Approach 1:
The patent combines multiple functions into the latch circuit, including data storage, signal transmission control, and voltage stabilization. By merging these functions into a single integrated circuit block, the design reduces the total number of separate elements while maintaining signal transmission accuracy and stability.
Solution Approach 2:
The latch circuit is designed to perform multiple functions: it latches data, transmits signals between bit lines, and stabilizes voltages during operations. This multi-functionality allows the circuit to replace what would traditionally require separate dedicated circuits, thereby reducing overall space occupation while maintaining performance.
2Ease of manufacture
If the page buffer structure is simplified, then fabrication costs decrease, but the reliability of signal transmission may be affected
Solution Approach 1:
By integrating voltage stabilization functionality directly into the latch circuit structure, the patent eliminates the need for separate voltage stabilization circuits. This merging reduces the total number of components and simplifies the fabrication process while maintaining signal transmission stability through the integrated design.
Solution Approach 2:
The latch circuit is designed to perform its own voltage stabilization function without requiring external assistance from separate circuits. The circuit uses its internal structure and operating characteristics to maintain stable voltage levels during data transmission, thereby simplifying the overall system while ensuring reliable signal transmission.
Data Source
AI summary
Examples of the present application disclose a page buffer including a plurality of latch circuits. Each latch circuit includes a resetting control circuit, a setting control circuit, a data transmission circuit, and a latch transmission circuit. The resetting control circuit is coupled to a first data node and configured to receive a first supply voltage, so as to determine a potential of the first data node. The setting control circuit is coupled to a second data node and configured to receive the first supply voltage, so as to determine a potential of the second data node. The data transmission circuit is coupled to the first data node and the second data node and configured to receive a second supply voltage. The latch transmission circuit is coupled to the first data node, the second data node, and a sense node. The first supply voltage is higher than the second supply voltage.