Nonvolatile Memory Core Bias Line Stabilization Circuit

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Solution Overview

Problem

The virtual negative read scheme in nonvolatile memory devices generates substantial noise when applying a positive bias to the source line and virtual power line, leading to distortion of the cell threshold voltage and deterioration of device characteristics.

Innovation Solution

A core bias line stabilization circuit is introduced, comprising a driving voltage generation unit, a comparison unit, and a compensation driving unit that compares the voltage level of the core bias line with predetermined limit levels and compensates by pull-up or pull-down driving to stabilize the voltage within target limits, minimizing noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a positive bias (VCORE) is applied to the source line and virtual power line in virtual negative read scheme, then the well separation of path transistor is eliminated and device complexity is reduced, but substantial noise is generated causing cell threshold voltage distortion

Engineering Contradiction:
Improvedevice complexityVSAvoidnoise
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a feedback mechanism through a stabilization circuit that includes a comparator and control transistor. The comparator continuously monitors the voltage level of the core bias line and compares it against a reference voltage, generating a control signal that activates the stabilization transistor to pull the core bias line voltage down when it exceeds the reference level. This feedback loop effectively suppresses noise while maintaining the simplified virtual negative read architecture.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If a positive bias (VCORE) is applied to the source line and virtual power line, then the read operation can be performed without negative bias, but noise generation leads to distortion of cell threshold voltage

Engineering Contradiction:
Improveease of operationVSAvoiddevice characteristics
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces an intermediary stabilization circuit between the core bias line and the rest of the circuitry. This circuit acts as a mediator that allows the positive bias to be applied for ease of operation while simultaneously filtering out noise through the voltage regulation mechanism. The stabilization transistor serves as a controlled intermediary that maintains voltage within acceptable limits, protecting the cell threshold voltage from distortion.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If the distribution of cell threshold voltage is widened due to circuit line width shrinkage, then more read operations can be performed, but the read operation in negative region becomes difficult

Engineering Contradiction:
ImproveproductivityVSAvoidease of operation
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

Instead of applying negative bias to the selected word line as in traditional negative read, the patent inverts the approach by applying positive bias to the source line and virtual power line. This inversion of the biasing strategy allows the system to handle widened cell threshold voltage distributions while maintaining ease of operation through the simplified virtual negative read scheme.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS8797809B2Nonvolatile memory device
Publication Date: 2014.08.05 SK HYNIX INC
  • US8797809B2 patent drawing
  • US8797809B2 patent drawing
  • US8797809B2 patent drawing

AI summary

A nonvolatile memory device includes: a driving voltage generation unit configured to generate a driving voltage of a core bias line included in a memory cell current path; a comparison unit configured to compare a voltage level of the core bias line with a predetermined limit level in response to a virtual negative read signal; and a compensation driving unit configured to compensation-drive the core bias line in response to an output signal of the comparison unit.